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SN74SSTVF16857VRG4 PDF预览

SN74SSTVF16857VRG4

更新时间: 2024-01-15 05:03:25
品牌 Logo 应用领域
德州仪器 - TI 光电二极管逻辑集成电路触发器电视
页数 文件大小 规格书
12页 333K
描述
14-Bit Registered Buffer With SSTL_2 Inputs and Outputs 48-TVSOP 0 to 70

SN74SSTVF16857VRG4 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:TSSOP, TSSOP48,.25,16针数:48
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.17系列:SSTV
JESD-30 代码:R-PDSO-G48JESD-609代码:e4
长度:9.7 mm逻辑集成电路类型:D FLIP-FLOP
湿度敏感等级:1位数:14
功能数量:1端子数量:48
最高工作温度:70 °C最低工作温度:
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP48,.25,16
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260电源:2.5 V
传播延迟(tpd):2.6 ns认证状态:Not Qualified
座面最大高度:1.2 mm子类别:Other Logic ICs
最大供电电压 (Vsup):2.7 V最小供电电压 (Vsup):2.3 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.4 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:4.4 mm最小 fmax:250 MHz
Base Number Matches:1

SN74SSTVF16857VRG4 数据手册

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SCES411B – AUGUST 2002 – REVISED APRIL 2003  
DGG PACKAGE  
(TOP VIEW)  
D
D
Member of the Texas Instruments  
Widebus Family  
Operates at 2.3 V to 2.7 V for PC1600,  
PC2100, and PC2700; 2.5 V to 2.7 V for  
PC3200  
Q1  
Q2  
GND  
D1  
D2  
GND  
V
D3  
D4  
D5  
D6  
D7  
1
2
3
4
5
6
7
8
9
48  
47  
46  
45  
44  
43  
42  
41  
40  
D
D
Pinout and Functionality Compatible With  
JEDEC Standard SSTV16857  
V
DDQ  
Q3  
CC  
600 ps Faster (Simultaneous Switching)  
Than JEDEC Standard SSTV16857 in  
PC2700 DIMM Applications  
Q4  
Q5  
GND  
V
D
D
D
D
D
Output Edge-Control Circuitry Minimizes  
Switching Noise in Unterminated DIMM  
Load  
DDQ  
Q6 10  
39 CLK  
Q7  
CLK  
V
11  
12  
38  
37  
V
DDQ  
CC  
Outputs Meet SSTL_2 Class I  
Specifications  
GND 13  
Q8 14  
Q9 15  
36 GND  
35  
V
REF  
Supports SSTL_2 Data Inputs  
34 RESET  
Differential Clock (CLK and CLK) Inputs  
V
16  
33 D8  
DDQ  
Supports LVCMOS Switching Levels on the  
RESET Input  
GND 17  
Q10 18  
Q11 19  
Q12 20  
32 D9  
31 D10  
30 D11  
29 D12  
D
RESET Input Disables Differential Input  
Receivers, Resets All Registers, and  
Forces All Outputs Low  
V
21  
28  
V
DDQ  
CC  
GND 22  
Q13 23  
Q14 24  
27 GND  
26 D13  
25 D14  
D
D
D
Flow-Through Architecture Optimizes PCB  
Layout  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
– 1000-V Charged-Device Model (C101)  
description/ordering information  
This 14-bit registered buffer is designed for 2.3-V to 2.7-V V  
operation.  
CC  
All inputs are SSTL_2, except the LVCMOS reset (RESET) input. All outputs are edge-controlled circuits  
optimized for unterminated DIMM loads and meet SSTL_2 Class I specifications.  
The SN74SSTVF16857 operates from a differential clock (CLK and CLK). Data are registered at the crossing  
of CLK going high and CLK going low.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
0°C to 70°C  
TSSOP – DGG Tape and reel SN74SSTVF16857GR  
SSTVF16857  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design  
guidelines are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments.  
Copyright 2003, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

SN74SSTVF16857VRG4 替代型号

型号 品牌 替代类型 描述 数据表
SN74SSTVF16857VR TI

完全替代

14 BIT REGISTERED BUFFER WITH SSTL 2 INPUT AND OUTPUTS
SN74SSTV16857DGVR TI

类似代替

14-BIT REGISTERED BUFFER WITH SSTL 2 INPUTS AND OUTPUTS

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