Datasheet > SN74SSTVF32852

SN74SSTVF32852

更新时间： 2024-02-29 13:05:35

品牌	Logo	应用领域
德州仪器 - TI		输出元件输入元件
页数	文件大小	规格书
11页	285K
描述
24-BIT TO 48-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND OUTPUTS

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SN74SSTVF32852 数据手册

SN74SSTVF32852

24-BIT TO 48-BIT REGISTERED BUFFER

WITH SSTL_2 INPUTS AND OUTPUTS

SCES426A – FEBRUARY 2003 – REVISED MARCH 2003

Member of the Texas Instruments

Widebus Family

Outputs Meet SSTL_2 Class I

Specifications

Operates at 2.3 V to 2.7 V for PC1600,

PC2100, and PC2700; 2.5 V to 2.7 V for

PC3200

Supports SSTL_2 Data Inputs

Differential Clock (CLK and CLK) Inputs

Supports LVCMOS Switching Levels on the

RESET Input

Pinout and Functionality Compatible With

JEDEC Standard SSTV32852

RESET Input Disables Differential Input

Receivers, Resets All Registers, and

Forces All Outputs Low

Pinout Optimizes 1U DDR DIMM Layout

600 ps Faster (Simultaneous Switching)

Than the JEDEC Standard SSTV32852 in

PC2700 DIMM Applications

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

1-to-2 Outputs Support Stacked DDR

DIMMs

ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

One Device Per DIMM Required

– 1000-V Charged-Device Model (C101)

Output Edge-Control Circuitry Minimizes

Switching Noise in an Unterminated Line

description/ordering information

This 24-bit to 48-bit registered buffer is designed for 2.3-V to 2.7-V V

operation.

All inputs are SSTL_2, except the LVCMOS reset (RESET) input. All outputs are edge-controlled circuits,

optimized for unterminated DIMM loads, and meet SSTL_2 Class I specifications.

The SN74SSTVF32852 operates from a differential clock (CLK and CLK). Data are registered at the crossing

of CLK going high and CLK going low.

The device supports low-power standby operation. When RESET is low, the differential input receivers are

disabled, and undriven (floating) data, clock, and reference voltage (V

) inputs are allowed. In addition, when

REF

RESET is low, all registers are reset and all outputs are forced low. The LVCMOS RESET input always must

be held at a valid logic high or low level.

To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in

the low state during power up.

ORDERING INFORMATION

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

†

PACKAGE

LFBGA – GKF

0°C to 70°C

Tape and reel SN74SSTVF32852KR

SVF852

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design

guidelines are available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...11

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与SN74SSTVF32852相关器件

型号	品牌	获取价格	描述	数据表
SN74SSTVF32852KR	TI	获取价格	24-BIT TO 48-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND OUTPUTS
SN74STV16857DGGRG4	TI	获取价格	14-Bit Registered Buffer With SSTL_2 Inputs and Outputs 48-TSSOP 0 to 70
SN74TVC16222	TI	获取价格	22-BIT VOLTAGE CLAMP
SN74TVC16222-1	TI	获取价格	10-BIT VOLTAGE CLAMP
SN74TVC16222-2	TI	获取价格	DUAL VOLTAGE CLAMP
SN74TVC16222A	TI	获取价格	22-BIT VOLTAGE CLAMP
SN74TVC16222A_07	TI	获取价格	22-BIT VOLTAGE CLAMP
SN74TVC16222A_08	TI	获取价格	22-BIT VOLTAGE CLAMP
SN74TVC16222ADGG	TI	获取价格	22-BIT VOLTAGE CLAMP
SN74TVC16222ADGGR	TI	获取价格	22-BIT VOLTAGE CLAMP

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