Datasheet > SN74SSTV32867-EP

SN74SSTV32867-EP

更新时间： 2024-11-23 12:21:43

品牌	Logo	应用领域
德州仪器 - TI		输出元件输入元件
页数	文件大小	规格书
11页	359K
描述
26-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND LVCMOS OUTPUTS

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SN74SSTV32867-EP 数据手册

SN74SSTV32867-EP

26-BIT REGISTERED BUFFER

WITH SSTL_2 INPUTS AND LVCMOS OUTPUTS

www.ti.com

SCES664–SEPTEMBER 2006

FEATURES

•

Controlled Baseline

•

Output Edge-Control Circuitry Minimizes

Switching Noise in an Unterminated DIMM

Load

– One Assembly/Test Site, One Fabrication

Site

•

Supports SSTL_2 Data Inputs

•

Extended Temperature Performance of –40°C

to 85°C

Differential Clock (CLK and CLK) Inputs

Enhanced Diminishing Manufacturing

Sources (DMS) Support

Supports LVCMOS Switching Levels on the

RESET Input

•

Enhanced Product Change Notification

•

RESET Input Disables Differential Input

Receivers, Resets All Registers, and Forces

All Outputs Low

(1)

Qualification Pedigree

Member of the Texas Instruments

Widebus+™ Family

•

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

(1) Component qualification in accordance with JEDEC and

industry standards to ensure reliable operation over an

extended temperature range. This includes, but is not limited

to, Highly Accelerated Stress Test (HAST) or biased 85/85,

temperature cycle, autoclave or unbiased HAST,

ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

electromigration, bond intermetallic life, and mold compound

life. Such qualification testing should not be viewed as

justifying use of this component beyond specified

performance and environmental limits.

– 1000-V Charged-Device Model (C101)

DESCRIPTION/ORDERING INFORMATION

This 26-bit registered buffer is designed for 2.3-V to 2.7-V V_CCoperation.

All inputs are SSTL_2, except the LVCMOS reset (RESET) input. All outputs are edge-controlled LVCMOS

circuits optimized for unterminated DIMM loads.

The SN74SSTV32867-EP operates from a differential clock (CLK and CLK). Data are registered at the crossing

of CLK going high and CLK going low.

The device supports low-power standby operation. When RESET is low, the differential input receivers are

disabled, and undriven (floating) data, clock, and reference voltage (V_REF) inputs are allowed. In addition, when

RESET is low, all registers are reset and all outputs are forced low. The LVCMOS RESET always must be held

at a valid logic high or low level.

To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the

low state during power up.

ORDERING INFORMATION

T_A

PACKAGE⁽¹⁾

ORDERABLE PART NUMBER

TOP-SIDE MARKING

S867EP

–40°C to 85°C

LFBGA – GKE

Tape and reel

CSSTV32867SGKEREP

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus+ is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

12 3 4 5 6 7...11

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SN74SSTVF16857VR	TI	获取价格	14 BIT REGISTERED BUFFER WITH SSTL 2 INPUT AND OUTPUTS
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