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SN74SSTV32877GKER PDF预览

SN74SSTV32877GKER

更新时间： 2024-01-07 06:09:20
品牌 Logo 应用领域
德州仪器 - TI 驱动逻辑集成电路电视
页数 文件大小 规格书
9页 163K
描述
26-Bit Registered Buffer with SSTL_2 Inputs and Outputs 96-LFBGA 0 to 70

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SN74SSTV32877GKER 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：BGA
包装说明：LFBGA, BGA96,6X16,32针数：96
Reach Compliance Code：not_compliantHTS代码：8542.39.00.01
Factory Lead Time：1 week风险等级：8.23
系列：SSTVJESD-30 代码：R-PBGA-B96
JESD-609代码：e0长度：13.5 mm
逻辑集成电路类型：BUS DRIVER湿度敏感等级：3
位数：26功能数量：1
端口数量：2端子数量：96
最高工作温度：70 °C最低工作温度：
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：LFBGA
封装等效代码：BGA96,6X16,32封装形状：RECTANGULAR
封装形式：GRID ARRAY, LOW PROFILE, FINE PITCH峰值回流温度（摄氏度）：220
电源：2.5 V传播延迟（tpd）：2.8 ns
认证状态：Not Qualified座面最大高度：1.4 mm
子类别：Other Logic ICs最大供电电压 (Vsup)：2.7 V
最小供电电压 (Vsup)：2.3 V标称供电电压 (Vsup)：2.5 V
表面贴装：YES温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：BALL
端子节距：0.8 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：5.5 mm
Base Number Matches：1

SN74SSTV32877GKER 数据手册

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SN74SSTV32877  
26-BIT REGISTERED BUFFER  
WITH SSTL_2 INPUTS AND OUTPUTS  
SCES378B – OCTOBER 2001 – REVISED MAY 2002  
Member of the Texas Instruments  
Widebus+ Family  
Flow-through Architecture Optimizes PCB  
Layout  
Supports SSTL_2 Data Inputs  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
Outputs Meet SSTL_2 Class II  
Specifications  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
Differential Clock Inputs (CLK and CLK)  
Supports LVCMOS Switching Levels on the  
RESET Input  
– 1000-V Charged-Device Model (C101)  
RESET Input Disables Differential Input  
Receivers, Resets All Registers, and  
Forces All Outputs Low  
description  
This 26-bit registered buffer is designed for 2.3-V to 2.7-V V  
operation.  
CC  
All inputs are SSTL_2, except the LVCMOS reset (RESET) input. All outputs are SSTL_2, Class II compatible.  
The SN74SSTV32877 operates from a differential clock (CLK and CLK). Data are registered at the crossing  
of CLK going high and CLK going low.  
The device supports low-power standby operation. When RESET is low, the differential input receivers are  
disabled, and undriven (floating) data, clock, and reference voltage (V  
RESET is low, all registers are reset and all outputs are forced low. The LVCMOS RESET input always must  
) inputs are allowed. In addition, when  
REF  
be held at a valid logic high or low level. When OE and RESET are high, the outputs are in the high-impedance  
state.  
To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in  
the low state during power up.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus+ is a trademark of Texas Instruments.  
Copyright 2002, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...9

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