Datasheet > SN74SSTV32877

SN74SSTV32877

更新时间： 2024-02-05 21:56:19

品牌	Logo	应用领域
德州仪器 - TI		输出元件输入元件
页数	文件大小	规格书
12页	392K
描述
26-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND OUTPUTS

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SN74SSTV32877 数据手册

SN74SSTV32877

26-BIT REGISTERED BUFFER

WITH SSTL_2 INPUTS AND OUTPUTS

SCES378B – OCTOBER 2001 – REVISED MAY 2002

Member of the Texas Instruments

Widebus+ Family

Flow-through Architecture Optimizes PCB

Layout

Supports SSTL_2 Data Inputs

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

Outputs Meet SSTL_2 Class II

Specifications

ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

Differential Clock Inputs (CLK and CLK)

Supports LVCMOS Switching Levels on the

RESET Input

– 1000-V Charged-Device Model (C101)

RESET Input Disables Differential Input

Receivers, Resets All Registers, and

Forces All Outputs Low

description

This 26-bit registered buffer is designed for 2.3-V to 2.7-V V

operation.

All inputs are SSTL_2, except the LVCMOS reset (RESET) input. All outputs are SSTL_2, Class II compatible.

The SN74SSTV32877 operates from a differential clock (CLK and CLK). Data are registered at the crossing

of CLK going high and CLK going low.

The device supports low-power standby operation. When RESET is low, the differential input receivers are

disabled, and undriven (floating) data, clock, and reference voltage (V

RESET is low, all registers are reset and all outputs are forced low. The LVCMOS RESET input always must

) inputs are allowed. In addition, when

REF

be held at a valid logic high or low level. When OE and RESET are high, the outputs are in the high-impedance

state.

To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in

the low state during power up.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus+ is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...12

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