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SN74SSTV32852ZKFR PDF预览

SN74SSTV32852ZKFR

更新时间： 2024-01-07 04:22:00
品牌 Logo 应用领域
德州仪器 - TI 触发器锁存器逻辑集成电路电视输出元件输入元件
页数 文件大小 规格书
10页 270K
描述
24-BIT TO 48-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND OUTPUTS

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SN74SSTV32852ZKFR 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Lifetime Buy零件包装代码：BGA
包装说明：LFBGA, BGA114,6X19,32针数：114
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：7.48
Is Samacsys：N系列：SSTV
JESD-30 代码：R-PBGA-B114JESD-609代码：e1
长度：16 mm逻辑集成电路类型：D FLIP-FLOP
最大频率@ Nom-Sup：200000000 Hz最大I（ol）：0.02 A
湿度敏感等级：3位数：24
功能数量：1端子数量：114
最高工作温度：70 °C最低工作温度：
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：LFBGA
封装等效代码：BGA114,6X19,32封装形状：RECTANGULAR
封装形式：GRID ARRAY, LOW PROFILE, FINE PITCH包装方法：TR
峰值回流温度（摄氏度）：260电源：2.5 V
Prop。Delay @ Nom-Sup：3.1 ns传播延迟（tpd）：3.1 ns
认证状态：Not Qualified座面最大高度：1.4 mm
子类别：Other Logic ICs最大供电电压 (Vsup)：2.7 V
最小供电电压 (Vsup)：2.3 V标称供电电压 (Vsup)：2.5 V
表面贴装：YES温度等级：COMMERCIAL
端子面层：Tin/Silver/Copper (Sn/Ag/Cu)端子形式：BALL
端子节距：0.8 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED触发器类型：POSITIVE EDGE
宽度：5.5 mm最小 fmax：200 MHz
Base Number Matches：1

SN74SSTV32852ZKFR 数据手册

 浏览型号SN74SSTV32852ZKFR的Datasheet PDF文件第2页浏览型号SN74SSTV32852ZKFR的Datasheet PDF文件第3页浏览型号SN74SSTV32852ZKFR的Datasheet PDF文件第4页浏览型号SN74SSTV32852ZKFR的Datasheet PDF文件第5页浏览型号SN74SSTV32852ZKFR的Datasheet PDF文件第6页浏览型号SN74SSTV32852ZKFR的Datasheet PDF文件第7页 
SN74SSTV32852  
24-BIT TO 48-BIT REGISTERED BUFFER  
WITH SSTL_2 INPUTS AND OUTPUTS  
SCES361C – AUGUST 2001 – REVISED FEBRUARY 2003  
Member of the Texas Instruments  
Widebus Family  
RESET Input Disables Differential Input  
Receivers, Resets All Registers, and  
Forces All Outputs Low  
1-to-2 Outputs Support Stacked DDR  
DIMMs  
Pinout Optimizes DIMM PCB Layout  
One Device Per DIMM Required  
Supports SSTL_2 Data Inputs  
Outputs Meet SSTL_2 Class II  
Specifications  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
Differential Clock (CLK and CLK) Inputs  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 1000-V Charged-Device Model (C101)  
Supports LVCMOS Switching Levels on the  
RESET Input  
description/ordering information  
This 24-bit to 48-bit registered buffer is designed for 2.3-V to 2.7-V V  
operation.  
CC  
All inputs are SSTL_2, except the LVCMOS reset (RESET) input. All outputs are SSTL_2, Class II compatible.  
The SN74SSTV32852 operates from a differential clock (CLK and CLK). Data are registered at the crossing  
of CLK going high and CLK going low.  
The device supports low-power standby operation. When RESET is low, the differential input receivers are  
disabled, and undriven (floating) data, clock, and reference voltage (V  
) inputs are allowed. In addition, when  
REF  
RESET is low, all registers are reset and all outputs are forced low. The LVCMOS RESET input always must  
be held at a valid logic high or low level.  
To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in  
the low state during power up.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
T
PACKAGE  
LFBGA – GKF  
A
0°C to 70°C  
Tape and reel SN74SSTV32852GKFR  
SV852  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design  
guidelines are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments.  
Copyright 2003, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...10

中文翻译

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SN74SSTV32852ZKFR 替代型号

型号 品牌 替代类型 描述 数据表
SN74SSTV32852GKFR TI

完全替代

 24-BIT TO 48-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND OUTPUTS
SN74SSTVF32852KR TI

类似代替

 24-BIT TO 48-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND OUTPUTS
74SSTVF32852ZKFR TI

类似代替

 24-BIT TO 48-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND OUTPUTS

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