SN74SSTV32852

更新时间： 2024-11-08 22:37:07

品牌	Logo	应用领域
德州仪器 - TI		输出元件输入元件
页数	文件大小	规格书
10页	270K
描述
24-BIT TO 48-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND OUTPUTS

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

SN74SSTV32852 数据手册

SN74SSTV32852

24-BIT TO 48-BIT REGISTERED BUFFER

WITH SSTL_2 INPUTS AND OUTPUTS

SCES361C – AUGUST 2001 – REVISED FEBRUARY 2003

Member of the Texas Instruments

Widebus Family

RESET Input Disables Differential Input

Receivers, Resets All Registers, and

Forces All Outputs Low

1-to-2 Outputs Support Stacked DDR

DIMMs

Pinout Optimizes DIMM PCB Layout

One Device Per DIMM Required

Supports SSTL_2 Data Inputs

Outputs Meet SSTL_2 Class II

Specifications

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

Differential Clock (CLK and CLK) Inputs

ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 1000-V Charged-Device Model (C101)

Supports LVCMOS Switching Levels on the

RESET Input

description/ordering information

This 24-bit to 48-bit registered buffer is designed for 2.3-V to 2.7-V V

operation.

All inputs are SSTL_2, except the LVCMOS reset (RESET) input. All outputs are SSTL_2, Class II compatible.

The SN74SSTV32852 operates from a differential clock (CLK and CLK). Data are registered at the crossing

of CLK going high and CLK going low.

The device supports low-power standby operation. When RESET is low, the differential input receivers are

disabled, and undriven (floating) data, clock, and reference voltage (V

) inputs are allowed. In addition, when

REF

RESET is low, all registers are reset and all outputs are forced low. The LVCMOS RESET input always must

be held at a valid logic high or low level.

To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in

the low state during power up.

ORDERING INFORMATION

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

†

PACKAGE

LFBGA – GKF

0°C to 70°C

Tape and reel SN74SSTV32852GKFR

SV852

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design

guidelines are available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...10

中文翻译

下载PDF

与SN74SSTV32852相关器件

型号	品牌	获取价格	描述	数据表
SN74SSTV32852_09	TI	获取价格	24-BIT TO 48-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND OUTPUTS
SN74SSTV32852-EP	TI	获取价格	24-BIT TO 48-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND OUTPUTS
SN74SSTV32852GKFR	TI	获取价格	24-BIT TO 48-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND OUTPUTS
SN74SSTV32852ZKFR	TI	获取价格	24-BIT TO 48-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND OUTPUTS
SN74SSTV32867-EP	TI	获取价格	26-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND LVCMOS OUTPUTS
SN74SSTV32877	TI	获取价格	26-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND OUTPUTS
SN74SSTV32877GKER	TI	获取价格	26-Bit Registered Buffer with SSTL_2 Inputs and Outputs 96-LFBGA 0 to 70
SN74SSTVF16857	TI	获取价格	14 BIT REGISTERED BUFFER WITH SSTL 2 INPUT AND OUTPUTS
SN74SSTVF16857_09	TI	获取价格	14 BIT REGISTERED BUFFER WITH SSTL 2 INPUT AND OUTPUTS
SN74SSTVF16857GR	TI	获取价格	14 BIT REGISTERED BUFFER WITH SSTL 2 INPUT AND OUTPUTS

与SN74SSTV32852相关文章

英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

22
苹果iPhone 17将全系采用三星/LG显示LTPO OLED面板
2024-11-05

21
三星深化印度制造布局，供应链本地化进程加速
2024-10-29

47
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

39

产品中心

服务支持

精选活动

关于我们

帮助中心

SN74SSTV32852

SN74SSTV32852 数据手册

与SN74SSTV32852相关器件

与SN74SSTV32852相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

SN74SSTV32852

SN74SSTV32852 数据手册

与SN74SSTV32852相关器件

与SN74SSTV32852相关文章

您还可以找

您在本页遇到什么问题？