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SN74SSTL16837ADGG

更新时间： 2024-11-23 22:16:47
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德州仪器 - TI 驱动器输出元件
页数 文件大小 规格书
6页 96K
描述
20-BIT SSTL_3 INTERFACE UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS

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SN74SSTL16837ADGG 数据手册

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SN74SSTL16837A  
20-BIT SSTL_3 INTERFACE UNIVERSAL BUS DRIVER  
WITH 3-STATE OUTPUTS  
SCBS675G – SEPTEMBER 1996 – REVISED SEPTEMBER 1998  
DGG PACKAGE  
(TOP VIEW)  
Member of the Texas Instruments  
Widebus Family  
Supports SSTL_3 Signal Inputs and  
Outputs  
Y1  
Y2  
GND  
Y3  
A1  
A2  
GND  
A3  
A4  
1
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
2
Flow-Through Architecture Optimizes PCB  
Layout  
3
4
Meets SSTL_3 Class I and Class II  
Specifications  
Y4  
5
V
V
6
DDQ  
Y5  
CC  
A5  
A6  
GND  
A7  
A8  
7
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
Y6  
GND  
Y7  
8
9
Packaged in Plastic Thin Shrink  
Small-Outline Package  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
Y8  
V
V
description  
DDQ  
Y9  
CC  
A9  
This 20-bit universal bus driver is designed for 3-V  
Y10  
GND  
OE  
A10  
GND  
CLK  
LE  
GND  
A11  
A12  
to 3.6-V V  
levels.  
operation and SSTL_3 or LVTTL I/O  
CC  
V
REF  
GND  
Data flow from A to Y is controlled by the  
output-enable (OE) input. The device operates in  
the transparent mode when latch enable (LE) is  
high. The A data is latched if LE is low and clock  
(CLK) is held at a high or low logic level. If LE is  
low, the A data is stored in the latch/flip-flop on the  
low-to-high transition of CLK. When OE is high,  
the outputs are in the high-impedance state.  
Y11  
Y12  
V
V
DDQ  
Y13  
CC  
A13  
A14  
GND  
A15  
A16  
Y14  
GND  
Y15  
To ensure the high-impedance state during power  
up or power down, OE should be tied to V  
through a pullup resistor; the minimum value of  
the resistor is determined by the current-sinking  
capability of the driver.  
Y16  
CC  
V
V
DDQ  
Y17  
CC  
A17  
A18  
GND  
A19  
A20  
Y18  
GND  
Y19  
The SN74SSTL16837A is characterized for  
operation from 0°C to 70°C.  
Y20  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments Incorporated.  
Copyright 1998, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
123456

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