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SN74SSTL16837ADGGR PDF预览

SN74SSTL16837ADGGR

更新时间: 2024-11-24 21:13:19
品牌 Logo 应用领域
德州仪器 - TI 驱动信息通信管理光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
6页 89K
描述
SSTL SERIES, 20-BIT DRIVER, TRUE OUTPUT, PDSO64, PLASTIC, TSSOP-64

SN74SSTL16837ADGGR 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP, TSSOP64,.32,20
针数:64Reach Compliance Code:unknown
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:7.9控制类型:ENABLE LOW
系列:SSTLJESD-30 代码:R-PDSO-G64
长度:17 mm负载电容(CL):30 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.02 A
位数:20功能数量:1
端口数量:2端子数量:64
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP64,.32,20封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3 V最大电源电流(ICC):90 mA
Prop。Delay @ Nom-Sup:4.2 ns传播延迟(tpd):3.2 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:BICMOS
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:6.1 mm
Base Number Matches:1

SN74SSTL16837ADGGR 数据手册

 浏览型号SN74SSTL16837ADGGR的Datasheet PDF文件第2页浏览型号SN74SSTL16837ADGGR的Datasheet PDF文件第3页浏览型号SN74SSTL16837ADGGR的Datasheet PDF文件第4页浏览型号SN74SSTL16837ADGGR的Datasheet PDF文件第5页浏览型号SN74SSTL16837ADGGR的Datasheet PDF文件第6页 
SN74SSTL16837A  
20-BIT SSTL_3 INTERFACE UNIVERSAL BUS DRIVER  
WITH 3-STATE OUTPUTS  
SCBS675G – SEPTEMBER 1996 – REVISED SEPTEMBER 1998  
DGG PACKAGE  
(TOP VIEW)  
Member of the Texas Instruments  
Widebus Family  
Supports SSTL_3 Signal Inputs and  
Outputs  
Y1  
Y2  
GND  
Y3  
A1  
A2  
GND  
A3  
A4  
1
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
2
Flow-Through Architecture Optimizes PCB  
Layout  
3
4
Meets SSTL_3 Class I and Class II  
Specifications  
Y4  
5
V
V
6
DDQ  
Y5  
CC  
A5  
A6  
GND  
A7  
A8  
7
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
Y6  
GND  
Y7  
8
9
Packaged in Plastic Thin Shrink  
Small-Outline Package  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
Y8  
V
V
description  
DDQ  
Y9  
CC  
A9  
This 20-bit universal bus driver is designed for 3-V  
Y10  
GND  
OE  
A10  
GND  
CLK  
LE  
GND  
A11  
A12  
to 3.6-V V  
levels.  
operation and SSTL_3 or LVTTL I/O  
CC  
V
REF  
GND  
Data flow from A to Y is controlled by the  
output-enable (OE) input. The device operates in  
the transparent mode when latch enable (LE) is  
high. The A data is latched if LE is low and clock  
(CLK) is held at a high or low logic level. If LE is  
low, the A data is stored in the latch/flip-flop on the  
low-to-high transition of CLK. When OE is high,  
the outputs are in the high-impedance state.  
Y11  
Y12  
V
V
DDQ  
Y13  
CC  
A13  
A14  
GND  
A15  
A16  
Y14  
GND  
Y15  
To ensure the high-impedance state during power  
up or power down, OE should be tied to V  
through a pullup resistor; the minimum value of  
the resistor is determined by the current-sinking  
capability of the driver.  
Y16  
CC  
V
V
DDQ  
Y17  
CC  
A17  
A18  
GND  
A19  
A20  
Y18  
GND  
Y19  
The SN74SSTL16837A is characterized for  
operation from 0°C to 70°C.  
Y20  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments Incorporated.  
Copyright 1998, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

SN74SSTL16837ADGGR 替代型号

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