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SN74SSTEB32866ZWLR

更新时间： 2024-09-16 12:21:43
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器触发器逻辑集成电路双倍数据速率
页数 文件大小 规格书
37页 1672K
描述
1.5V/1.8V 25-BIT CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST

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SN74SSTEB32866ZWLR 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Active零件包装代码：BGA
包装说明：BGA-96针数：96
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：8 weeks
风险等级：1.75Is Samacsys：N
其他特性：ALSO OPERATES AT 1.8 V SUPPLY计数方向：UNIDIRECTIONAL
系列：SSTEJESD-30 代码：R-PBGA-B96
JESD-609代码：e1长度：13.5 mm
逻辑集成电路类型：BUS DRIVER湿度敏感等级：3
位数：25功能数量：1
端口数量：2端子数量：96
最高工作温度：85 °C最低工作温度：-40 °C
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：LFBGA封装等效代码：BGA96,6X16,32
封装形状：RECTANGULAR封装形式：GRID ARRAY, LOW PROFILE, FINE PITCH
包装方法：TR峰值回流温度（摄氏度）：260
电源：1.5/1.8 V传播延迟（tpd）：1.7 ns
认证状态：Not Qualified座面最大高度：1.3 mm
子类别：Other Logic ICs最大供电电压 (Vsup)：1.575 V
最小供电电压 (Vsup)：1.425 V标称供电电压 (Vsup)：1.5 V
表面贴装：YES温度等级：INDUSTRIAL
端子面层：Tin/Silver/Copper (Sn/Ag/Cu)端子形式：BALL
端子节距：0.8 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED翻译：N/A
触发器类型：POSITIVE EDGE宽度：5.5 mm
Base Number Matches：1

SN74SSTEB32866ZWLR 数据手册

 浏览型号SN74SSTEB32866ZWLR的Datasheet PDF文件第2页浏览型号SN74SSTEB32866ZWLR的Datasheet PDF文件第3页浏览型号SN74SSTEB32866ZWLR的Datasheet PDF文件第4页浏览型号SN74SSTEB32866ZWLR的Datasheet PDF文件第5页浏览型号SN74SSTEB32866ZWLR的Datasheet PDF文件第6页浏览型号SN74SSTEB32866ZWLR的Datasheet PDF文件第7页 
SN74SSTEB32866  
www.ti.com ..................................................................................................................................................................................................... SCAS851–APRIL 2009  
1.5V/1.8V 25-BIT CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST  
1
FEATURES  
•
•
•
Supports 1.5V and 1.8V Supply Voltage Range  
Differential Clock (CLK and CLK) Inputs  
2
•
Member of the Texas Instruments Widebus+™  
Family  
Supports LVCMOS Switching Levels on the  
Control and RESET Inputs  
•
•
Pinout Optimizes DDR2 DIMM PCB Layout  
Configurable as 25-Bit 1:1 or 14-Bit 1:2  
Registered Buffer  
•
•
•
Checks Parity on DIMM-Independent Data  
Inputs  
•
•
Chip-Select Inputs Gate the Data Outputs from  
Changing State and Minimizes System Power  
Consumption  
Able to Cascade With a Second  
SN74SSTEB32866  
Supports Industrial Temperature Range (–40°C  
to 85°C)  
Output Edge-Control Circuitry Minimizes  
Switching Noise in an Unterminated Line  
DESCRIPTION  
This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.425-V to 1.9-V VCC operation. In the  
1:1 pinout configuration, only one device per DIMM is required to drive nine SDRAM loads. In the 1:2 pinout  
configuration, two devices per DIMM are required to drive 18 SDRAM loads.  
All inputs are SSTL_18, except the reset (RESET) and control (Cn) inputs, which are LVCMOS. All outputs are  
edge-controlled circuits optimized for unterminated DIMM loads and meets SSTL_18 and SSTL_15 specifications  
(depending on Supply voltage level), except the open-drain error (QERR) output.  
The SN74SSTEB32866 operates from a differential clock (CLK and CLK). Data are registered at the crossing of  
CLK going high and CLK going low.  
The SN74SSTEB32866 accepts a parity bit from the memory controller on the parity bit (PAR_IN) input,  
compares it with the data received on the DIMM-independent D-inputs (D2–D3, D5–D6, D8–D25 when C0 = 0  
and C1 = 0; D2–D3, D5–D6, D8–D14 when C0 = 0 and C1 = 1; or D1-D6, D8-D13 when C0 = 1 and C1 = 1) and  
indicates whether a parity error has occurred on the open-drain QERR pin (active low). The convention is even  
parity; i.e., valid parity is defined as an even number of ones across the DIMM-independent data inputs,  
combined with the parity input bit. To calculate parity, all DIMM-independent data inputs must be tied to a known  
logic state.  
When used as a single device, the C0 and C1 inputs are tied low. In this configuration, parity is checked on the  
PAR_IN input signal, which arrives one cycle after the input data to which it applies. Two clock cycles after the  
data are registered, the corresponding partial-parity-out (PPO) and QERR signals are generated.  
When used in pairs, the C0 input of the first register is tied low, and the C0 input of the second register is tied  
high. The C1 input of both registers are tied high. Parity, which arrives one cycle after the data input to which it  
applies, is checked on the PAR_IN input signal of the first device. Two clock cycles after the data are registered,  
the corresponding PPO and QERR signals are generated on the second device. The PPO output of the first  
register is cascaded to the PAR_IN of the second SN74SSTEB32866. The QERR output of the first  
SN74SSTEB32866 is left floating, and the valid error information is latched on the QERR output of the second  
SN74SSTEB32866.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
TOP-SIDE MARKING  
–40°C to 85°C  
LFBGA–ZWL  
Tape and reel  
SN74SSTEB32866ZWLR  
SEB866  
(1) Package drawings, packing quantities, thermal data, symbolization, PCB design guidelines available at www.ti.com/sc/package.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
Widebus+ is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2009, Texas Instruments Incorporated  
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