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SN74SSQEC32882ZALR PDF预览

SN74SSQEC32882ZALR

更新时间： 2024-11-06 12:21:43
品牌 Logo 应用领域
德州仪器 - TI 时钟驱动器测试
页数 文件大小 规格书
9页 498K
描述
28-Bit to 56-Bit Registered Buffer With Address Parity Test One Pair to Four Pair Differential Clock PLL Driver

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SN74SSQEC32882ZALR 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：BGA
包装说明：TFBGA, BGA176,11X20,25针数：176
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：1.8系列：SSQE
输入调节：DIFFERENTIALJESD-30 代码：R-PBGA-B176
JESD-609代码：e1长度：13.5 mm
逻辑集成电路类型：PLL BASED CLOCK DRIVER湿度敏感等级：3
功能数量：1反相输出次数：
端子数量：176实输出次数：4
最高工作温度：85 °C最低工作温度：
输出特性：OPEN-DRAIN封装主体材料：PLASTIC/EPOXY
封装代码：TFBGA封装等效代码：BGA176,11X20,25
封装形状：RECTANGULAR封装形式：GRID ARRAY, THIN PROFILE, FINE PITCH
包装方法：TR峰值回流温度（摄氏度）：250
电源：1.25/1.5 V认证状态：Not Qualified
座面最大高度：1.2 mm子类别：Other Logic ICs
标称供电电压 (Vsup)：1.5 V表面贴装：YES
技术：CMOS温度等级：OTHER
端子面层：Tin/Silver/Copper (Sn/Ag/Cu)端子形式：BALL
端子节距：0.65 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：8 mm
最小 fmax：945 MHz

SN74SSQEC32882ZALR 数据手册

 浏览型号SN74SSQEC32882ZALR的Datasheet PDF文件第2页浏览型号SN74SSQEC32882ZALR的Datasheet PDF文件第3页浏览型号SN74SSQEC32882ZALR的Datasheet PDF文件第4页浏览型号SN74SSQEC32882ZALR的Datasheet PDF文件第5页浏览型号SN74SSQEC32882ZALR的Datasheet PDF文件第6页浏览型号SN74SSQEC32882ZALR的Datasheet PDF文件第7页 
SN74SSQEC32882  
www.ti.com  
SCAS920-PUB –NOVEMBER 2011  
28-Bit to 56-Bit Registered Buffer With Address Parity Test  
One Pair to Four Pair Differential Clock PLL Driver  
Check for Samples: SN74SSQEC32882  
1
FEATURES  
(CS-Gated) Data Inputs  
•
•
•
Configurable Driver Strength  
Uses Internal Feedback Loop  
Optimized Power Consumption  
•
•
JEDEC SSTE32882  
1-to-2 Register Outputs and 1-to-4 Clock Pair  
Outputs Support Stacked DDR3 RDIMMs  
•
•
CKE Powerdown Mode for Optimized System  
Power Consumption  
APPLICATIONS  
1.5V/1.35V/1.25V Phase Lock Loop Clock  
Driver for Buffering One Differential Clock Pair  
(CK and CK) and Distributing to Four  
Differential Outputs  
•
•
•
•
DDR3 Registered DIMMs up to DDR3-1866  
DDR3L Registered DIMMs up to DDR3L-1600  
DDR3U Registered DIMMs up to DDR3U-1333  
Single-, Dual- and Quad-Rank RDIMM  
•
•
1.5V/1.35V/1.25V CMOS Inputs  
Checks Parity on Command and Address  
DESCRIPTION  
This 1:2 or 26-bit 1:2 and 4-bit 1:1 registering clock driver with parity is designed for operation on DDR3  
registered DIMMs with VDD of 1.5 V, on DDR3L registered DIMMs with VDD of 1.35 V and on DDR3U registered  
DIMMs with VDD of 1.25 V.  
All inputs are 1.5 V, 1.35V and 1.25 V CMOS compatible. All outputs are CMOS drivers optimized to drive DRAM  
signals on terminated traces in DDR3 RDIMM applications. The clock outputs Yn and Yn and control net outputs  
DxCKEn, DxCSn and DxODTn can be driven with a different strength and skew to optimize signal integrity,  
compensate for different loading and equalize signal travel speed.  
The SN74SSQEC32882 has two basic modes of operation associated with the Quad Chip Select Enable  
(QCSEN) input. When the QCSEN input pin is open (or pulled high), the component has two chip select inputs,  
DCS0 and DCS1, and two copies of each chip select output, QACS0, QACS1, QBCS0 and QBCS1. This is the  
"QuadCS disabled" mode. When the QCSEN input pin is pulled low, the component has four chip select inputs  
DCS[3:0], and four chip select outputs, QCS[3:0]. This is the "QuadCS enabled" mode. Through the remainder of  
this specification, DCS[n:0] will indicate all of the chip select inputs, where n=1 for QuadCS disabled, and n=3 for  
QuadCS enabled. QxCS[n:0] will indicate all of the chip select outputs.  
The device also supports a mode where a single device can be mounted on the back side of a DIMM. If  
MIRROR=HIGH, Input Bus Termination (IBT) has to stay enabled for all input signals in this case.  
The SN74SSQEC32882 operates from a differential clock (CK and CK). Data are registered at the crossing of  
CK going HIGH, and CK going LOW. This data could be either re-driven to the outputs or it could be used to  
access device internal control registers.  
The input bus data integrity is protected by a parity function. All address and command input signals are added  
up and the last bit of the sum is compared to the parity signal delivered by the system at the input PAR_IN one  
clock cycle later. If they do not match the device pulls the open drain output ERROUT LOW. The control signals  
(DCKE0, DCKE1, DODT0, DODT1, DCS[n:0]) are not part of this computation.  
The SN74SSQEC32882 implements different power saving mechanisms to reduce thermal power dissipation and  
to support system power down states. By disabling unused outputs the power consumption is further reduced.  
The package is optimized to support high density DIMMs. By aligning input and output positions towards DIMM  
finger signal ordering and SDRAM ballout the device de-scrambles the DIMM traces allowing low cross talk  
design with low interconnect latency.  
Edge controlled outputs reduce ringing and improve signal eye opening at the SDRAM inputs.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2011, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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