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SN74LVC2G125DCURE4 PDF预览

SN74LVC2G125DCURE4

更新时间： 2024-09-20 15:52:19
品牌 Logo 应用领域
德州仪器 - TI 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
13页 330K
描述
IC,BUFFER/DRIVER,SINGLE,2-BIT,LCX/LVC-CMOS,TSSOP,8PIN,PLASTIC

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SN74LVC2G125DCURE4 技术参数

生命周期：Obsolete包装说明：VSSOP, TSSOP8,.12,20
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.63控制类型：ENABLE LOW
系列：LVC/LCX/ZJESD-30 代码：R-PDSO-G8
长度：2.3 mm负载电容（CL）：50 pF
逻辑集成电路类型：BUS DRIVER最大I（ol）：0.024 A
位数：1功能数量：2
端口数量：2端子数量：8
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：VSSOP
封装等效代码：TSSOP8,.12,20封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, VERY THIN PROFILE, SHRINK PITCH包装方法：TAPE AND REEL
电源：3.3 VProp。Delay @ Nom-Sup：4.3 ns
传播延迟（tpd）：9.1 ns认证状态：Not Qualified
座面最大高度：0.9 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：1.65 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.5 mm
端子位置：DUAL宽度：2 mm
Base Number Matches：1

SN74LVC2G125DCURE4 数据手册

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SCES204K − APRIL 1999 − REVISED SEPTEMBER 2003  
DCT OR DCU PACKAGE  
(TOP VIEW)  
D
Available in the Texas Instruments  
NanoStarand NanoFreePackages  
D
D
D
D
D
D
Supports 5-V V  
Operation  
CC  
1OE  
1A  
2Y  
V
CC  
2OE  
1Y  
2A  
1
2
3
4
8
7
6
5
Inputs Accept Voltages to 5.5 V  
Max t of 4.3 ns at 3.3 V  
pd  
Low Power Consumption, 10-µA Max I  
GND  
CC  
24-mA Output Drive at 3.3 V  
YEA, YEP, YZA, OR YZP PACKAGE  
(BOTTOM VIEW)  
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
= 3.3 V, T = 25°C  
OLP  
CC  
A
D
D
D
D
Typical V  
(Output V  
Undershoot)  
OHV  
OH  
4 5  
3 6  
2 7  
1 8  
GND  
2Y  
1A  
2A  
1Y  
2OE  
>2 V at V  
= 3.3 V, T = 25°C  
CC  
A
I
Supports Partial-Power-Down Mode  
off  
Operation  
1OE  
V
CC  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
− 1000-V Charged-Device Model (C101)  
description/ordering information  
The SN74LVC2G125 is a dual bus buffer gate, designed for 1.65-V to 5.5-V V  
operation. This device features  
CC  
dual line drivers with 3-state outputs. The outputs are disabled when the associated output-enable (OE) input  
is high.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
T
A
PACKAGE  
‡
NanoStar− WCSP (DSBGA)  
0.17-mm Small Bump − YEA  
SN74LVC2G125YEAR  
SN74LVC2G125YZAR  
SN74LVC2G125YEPR  
SN74LVC2G125YZPR  
NanoFree− WCSP (DSBGA)  
0.17-mm Small Bump − YZA (Pb-free)  
Reel of 3000  
_ _ _CM_  
NanoStar− WCSP (DSBGA)  
0.23-mm Large Bump − YEP  
−40°C to 85°C  
NanoFree− WCSP (DSBGA)  
0.23-mm Large Bump − YZP (Pb-free)  
SSOP − DCT  
Reel of 3000  
Reel of 3000  
SN74LVC2G125DCTR  
SN74LVC2G125DCUR  
C25_ _ _  
C25_  
VSSOP − DCU  
Reel of 250  
SN74LVC2G125DCUT  
†
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.  
DCU: The actual top-side marking has one additional character that designates the assembly/test site.  
YEA/YZA, YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code,  
and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition  
(1 = SnPb, • = Pb-free).  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoStar and NanoFree are trademarks of Texas Instruments.  
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Copyright 2003, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...13

中文翻译

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