Datasheet > SN74LVC2G126_08

SN74LVC2G126_08

更新时间： 2024-02-20 16:58:52

品牌	Logo	应用领域
德州仪器 - TI		输出元件
页数	文件大小	规格书
12页	431K
描述
DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS

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SN74LVC2G126_08 数据手册

SN74LVC2G126

DUAL BUS BUFFER GATE

WITH 3-STATE OUTPUTS

www.ti.com

SCES205J–APRIL 1999–REVISED JANUARY 2007

FEATURES

•

Available in the Texas Instruments

NanoFree™ Package

•

I_offSupports Partial-Power-Down Mode

Operation

•

Supports 5-V V_CCOperation

Inputs Accept Voltages to 5.5 V

Max t_pdof 4 ns at 3.3 V

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

ESD Protection Exceeds JESD 22

–

2000-V Human-Body Model (A114-A)

200-V Machine Model (A115-A)

Low Power Consumption, 10-µA Max I_CC

±24-mA Output Drive at 3.3 V

1000-V Charged-Device Model (C101)

Typical V_OLP(Output Ground Bounce)

<0.8 V at V_CC= 3.3 V, T_A= 25°C

•

Typical V_OHV(Output V_OHUndershoot)

>2 V at V_CC= 3.3 V, T_A= 25°C

DCT PACKAGE

(TOP VIEW)

DCU PACKAGE

(TOP VIEW)

YZP PACKAGE

(BOTTOM VIEW)

4 5

GND

V_CC

2OE

1OE

V_CC

2OE

1OE

3 6

2 7

1 8

2OE

V_CC

1OE

GND

See mechanical drawings for dimensions.

DESCRIPTION/ORDERING INFORMATION

This dual bus buffer gate is designed for 1.65-V to 5.5-V V_CCoperation.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the

package.

The SN74LVC2G126 is a dual bus driver/line driver with 3-state outputs. The outputs are disabled when the

associated output-enable (OE) input is low.

To ensure the high-impedance state during power up or power down, OE should be tied to GND through a

pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the

driver.

ORDERING INFORMATION

T_A

PACKAGE⁽¹⁾

ORDERABLE PART NUMBER TOP-SIDE MARKING⁽²⁾

NanoFree™ – WCSP (DSBGA)

0.23-mm Large Bump – YZP (Pb-free)

SSOP – DCT

Reel of 3000

SN74LVC2G126YZPR

_ _ _CN_

C26_ _ _

Reel of 3000

Reel of 250

SN74LVC2G126DCTR

SN74LVC2G126DCUR

SN74LVC2G126DCUT

–40°C to 85°C

VSSOP – DCU

C26_

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

(2) DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.

DCU: The actual top-side marking has one additional character that designates the assembly/test site.

YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following

character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

NanoFree is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

12 3 4 5 6 7...12

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与SN74LVC2G126_08相关器件

型号	品牌	获取价格	描述	数据表
SN74LVC2G126BDCT	TI	获取价格	LVC/LCX/Z SERIES, DUAL 1-BIT DRIVER, TRUE OUTPUT, PDSO8
SN74LVC2G126DCT	TI	获取价格	LVC/LCX/Z SERIES, DUAL 1-BIT DRIVER, TRUE OUTPUT, PDSO8, PLASTIC, TSSOP-8
SN74LVC2G126DCTR	TI	获取价格	DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS
SN74LVC2G126DCU	TI	获取价格	LVC/LCX/Z SERIES, DUAL 1-BIT DRIVER, TRUE OUTPUT, PDSO8, PLASTIC, TSSOP-8
SN74LVC2G126DCUR	TI	获取价格	DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS
SN74LVC2G126DCUT	TI	获取价格	DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS
SN74LVC2G126-EP	TI	获取价格	具有三态输出的增强型产品 2 通道、1.65V 至 5.5V 缓冲器
SN74LVC2G126YEAR	TI	获取价格	DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS
SN74LVC2G126YEPR	TI	获取价格	DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS
SN74LVC2G126YZAR	TI	获取价格	DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS

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