Datasheet > 逻辑 > 总线驱动器/收发器> SN74LVC2G126YEPR

SN74LVC2G126YEPR

更新时间： 2024-11-18 22:09:51

品牌	Logo	应用领域
德州仪器 - TI		输出元件
页数	文件大小	规格书
13页	333K
描述
DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS

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中文翻译

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数据手册
替代型号

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SN74LVC2G126YEPR 数据手册

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SCES205H − APRIL 1999 − REVISED SEPTEMBER 2003

DCT OR DCU PACKAGE

(TOP VIEW)

Available in the Texas Instruments

NanoStar and NanoFree Packages

Supports 5-V V

Operation

1OE

2OE

Inputs Accept Voltages to 5.5 V

Max t of 4 ns at 3.3 V

Low Power Consumption, 10-µA Max I

GND

24-mA Output Drive at 3.3 V

YEA, YEP, YZA, OR YZP PACKAGE

(BOTTOM VIEW)

Typical V

<0.8 V at V

(Output Ground Bounce)

= 3.3 V, T = 25°C

OLP

Typical V

(Output V

Undershoot)

4 5

3 6

2 7

1 8

GND

2OE

OHV

>2 V at V

= 3.3 V, T = 25°C

Supports Partial-Power-Down Mode

off

1OE

Operation

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

ESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

− 1000-V Charged-Device Model (C101)

description/ordering information

This dual bus buffer gate is designed for 1.65-V to 5.5-V V

operation.

NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the

die as the package.

ORDERING INFORMATION

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

†

PACKAGE

‡

NanoStar − WCSP (DSBGA)

0.17-mm Small Bump − YEA

SN74LVC2G126YEAR

SN74LVC2G126YZAR

SN74LVC2G126YEPR

SN74LVC2G126YZPR

NanoFree − WCSP (DSBGA)

0.17-mm Small Bump − YZA (Pb-free)

Reel of 3000

_ _ _CN_

NanoStar − WCSP (DSBGA)

0.23-mm Large Bump − YEP

−40°C to 85°C

NanoFree − WCSP (DSBGA)

0.23-mm Large Bump − YZP (Pb-free)

SSOP − DCT

Reel of 3000

SN74LVC2G126DCTR

SN74LVC2G126DCUR

C26_ _ _

C26_

VSSOP − DCU

Reel of 250

SN74LVC2G126DCUT

†

‡

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.

DCU: The actual top-side marking has one additional character that designates the assembly/test site.

YEA/YZA,YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code,

and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition

^{(1 = SnPb,}• = Pb-free).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

NanoStar and NanoFree are trademarks of Texas Instruments.

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...13

中文翻译

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SN74LVC2G126YEPR 替代型号

型号	品牌	替代类型	描述	数据表
SN74LVC2G126YEAR	TI	功能相似	DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS
SN74LVC2G126YZAR	TI	功能相似	DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS

与SN74LVC2G126YEPR相关器件

型号	品牌	获取价格	描述	数据表
SN74LVC2G126YZAR	TI	获取价格	DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS
SN74LVC2G126YZPR	TI	获取价格	DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS
SN74LVC2G132	TI	获取价格	DUAL 2-INPUT NAND GATE WITH SCHMITT-TRIGGER INPUTS
SN74LVC2G132_07	TI	获取价格	DUAL 2-INPUT NAND GATE WITH SCHMITT-TRIGGER INPUTS
SN74LVC2G132_16	TI	获取价格	Dual 2-Input NAND Gate With Schmitt-Trigger Inputs
SN74LVC2G132DCTR	TI	获取价格	DUAL 2-INPUT NAND GATE WITH SCHMITT-TRIGGER INPUTS
SN74LVC2G132DCUR	TI	获取价格	DUAL 2-INPUT NAND GATE WITH SCHMITT-TRIGGER INPUTS
SN74LVC2G132DCUT	TI	获取价格	DUAL 2-INPUT NAND GATE WITH SCHMITT-TRIGGER INPUTS
SN74LVC2G132YEPR	TI	获取价格	DUAL 2-INPUT NAND GATE WITH SCHMITT-TRIGGER INPUTS
SN74LVC2G132YZPR	TI	获取价格	DUAL 2-INPUT NAND GATE WITH SCHMITT-TRIGGER INPUTS

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