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SN74LVC2G132DCUR PDF预览

SN74LVC2G132DCUR

更新时间： 2024-02-16 03:28:47
品牌 Logo 应用领域
德州仪器 - TI 触发器输入元件
页数 文件大小 规格书
13页 238K
描述
DUAL 2-INPUT NAND GATE WITH SCHMITT-TRIGGER INPUTS

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SN74LVC2G132DCUR 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：BGA
包装说明：VFBGA, BGA8,2X4,20针数：8
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：1.49系列：LVC/LCX/Z
JESD-30 代码：R-PBGA-B8JESD-609代码：e1
长度：1.9 mm负载电容（CL）：50 pF
逻辑集成电路类型：NAND GATE最大I（ol）：0.032 A
湿度敏感等级：1功能数量：2
输入次数：2端子数量：8
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：VFBGA
封装等效代码：BGA8,2X4,20封装形状：RECTANGULAR
封装形式：GRID ARRAY, VERY THIN PROFILE, FINE PITCH包装方法：TR
峰值回流温度（摄氏度）：260电源：3.3 V
最大电源电流（ICC）：0.01 mAProp。Delay @ Nom-Sup：6 ns
传播延迟（tpd）：16 ns认证状态：Not Qualified
施密特触发器：YES座面最大高度：0.5 mm
子类别：Gate最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：1.65 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：BALL端子节距：0.5 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：0.9 mmBase Number Matches：1

SN74LVC2G132DCUR 数据手册

 浏览型号SN74LVC2G132DCUR的Datasheet PDF文件第2页浏览型号SN74LVC2G132DCUR的Datasheet PDF文件第3页浏览型号SN74LVC2G132DCUR的Datasheet PDF文件第4页浏览型号SN74LVC2G132DCUR的Datasheet PDF文件第5页浏览型号SN74LVC2G132DCUR的Datasheet PDF文件第6页浏览型号SN74LVC2G132DCUR的Datasheet PDF文件第7页 
SN74LVC2G132  
DUAL 2-INPUT NAND GATE  
WITH SCHMITT-TRIGGER INPUTS  
www.ti.com  
SCES547A–FEBRUARY 2004–REVISED JUNE 2005  
FEATURES  
DCT OR DCU PACKAGE  
(TOP VIEW)  
•
Available in Texas Instruments NanoStar™  
and NanoFree™ Packages  
1
2
3
4
8
7
6
5
1A  
1B  
2Y  
V
CC  
•
•
•
•
•
•
Supports 5-V VCC Operation  
1Y  
2B  
2A  
Inputs Accept Voltages to 5.5 V  
Max tpd of 5.3 ns at 3.3 V  
GND  
Low Power Consumption, 10-µA Max ICC  
±24-mA Output Drive at 3.3 V  
YEP OR YZP PACKAGE  
(BOTTOM VIEW)  
Typical VOLP (Output Ground Bounce) <0.8 V  
at VCC = 3.3 V, TA = 25°C  
4
3
2
1
5
6
7
8
GND  
2Y  
2A  
2B  
1Y  
•
•
•
•
Typical VOHV (Output VOH Undershoot) >2 V at  
VCC = 3.3 V, TA = 25°C  
1B  
1A  
Ioff Supports Partial-Power-Down Mode  
Operation  
V
CC  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
– 1000-V Charged-Device Model (C101)  
DESCRIPTION/ORDERING INFORMATION  
This dual 2-input NAND gate with Schmitt-trigger inputs is designed for 1.65-V to 5.5-V VCC operation.  
The SN74LVC2G132 contains two inverters and performs the Boolean function Y = A B or Y = A + B in positive  
logic. The device functions as two independent inverters, but because of Schmitt action, it has different input  
threshold levels for positive-going (VT+) and negative-going (VT-) signals.  
NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the  
die as the package.  
This device can be triggered from the slowest of input ramps and still give clean jitter-free output signals.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
TOP-SIDE MARKING(2)  
NanoStar™ – WCSP (DSBGA)  
0.23-mm Large Bump – YEP  
SN74LVC2G132YEPR  
Reel of 3000  
_ _ _D5_  
NanoFree™ – WCSP (DSBGA)  
0.23-mm Large Bump – YZP  
(Pb-free)  
SN74LVC2G132YZPR  
–40°C to 85°C  
SSOP – DCT  
Reel of 3000 SN74LVC2G132DCTR  
Reel of 3000 SN74LVC2G132DCUR  
C3B_ _ _  
C3B_  
VSSOP – DCU  
Reel of 250  
SN74LVC2G132DCUT  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
(2) DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.  
DCU: The actual top-side marking has one additional character that designates the assembly/test site.  
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following  
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, = Pb-free).  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoStar, NanoFree are trademarks of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2004–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...13

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SN74LVC2G132DCUR 替代型号

型号 品牌 替代类型 描述 数据表
74LVC2G132DCUTE4 TI

完全替代

 DUAL 2-INPUT NAND GATE WITH SCHMITT-TRIGGER INPUTS
74LVC2G132DCURE4 TI

类似代替

 DUAL 2-INPUT NAND GATE WITH SCHMITT-TRIGGER INPUTS

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