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SN74LVC2G14_08 PDF预览

SN74LVC2G14_08

更新时间： 2024-02-12 07:46:57
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德州仪器 - TI 触发器
页数 文件大小 规格书
15页 432K
描述
DUAL SCHMITT-TRIGGER INVERTER

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SN74LVC2G14_08 数据手册

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SN74LVC240A  
OCTAL BUFFER/DRIVER  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCAS293K–JANUARY 1993–REVISED FEBRUARY 2005  
FEATURES  
DB, DGV, DW, NS, OR PW PACKAGE  
(TOP VIEW)  
•
•
•
•
Operates From 1.65 V to 3.6 V  
Inputs Accept Voltages to 5.5 V  
Max tpd of 6.5 ns at 3.3 V  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
1OE  
1A1  
2Y4  
1A2  
2Y3  
1A3  
2Y2  
1A4  
2Y1  
GND  
V
CC  
2OE  
1Y1  
2A4  
1Y2  
2A3  
1Y3  
2A2  
1Y4  
2A1  
Typical VOLP (Output Ground Bounce)  
<0.8 V at VCC = 3.3 V, TA = 25°C  
•
•
Typical VOHV (Output VOH Undershoot)  
>2 V at VCC = 3.3 V, TA = 25°C  
Supports Mixed-Mode Signal Operation on All  
Ports (5-V Input/Output Voltage With  
3.3-V VCC  
)
•
•
•
Ioff Supports Partial-Power-Down-Mode  
Operation  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
– 1000-V Charged-Device Model (C101)  
DESCRIPTION/ORDERING INFORMATION  
This octal buffer/driver is designed for 1.65-V to 3.6-V VCC operation.  
The SN74LVC240A is designed specifically to improve the performance and density of 3-state memory address  
drivers, clock drivers, and bus-oriented receivers and transmitters.  
This device is organized as two 4-bit buffers/drivers with separate output-enable (OE) inputs. When OE is low,  
the device passes data from the A inputs to the Y outputs. When OE is high, the outputs are in the  
high-impedance state.  
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in  
a mixed 3.3-V/5-V system environment.  
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,  
preventing damaging current backflow through the device when it is powered down.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
SN74LVC240ADW  
TOP-SIDE MARKING  
Tube of 25  
SOIC – DW  
LVC240A  
Reel of 2000  
Reel of 2000  
Reel of 2000  
Tube of 70  
SN74LVC240ADWR  
SN74LVC240ANSR  
SN74LVC240ADBR  
SN74LVC240APW  
SOP – NS  
LVC240A  
LC240A  
SSOP – DB  
–40°C to 85°C  
TSSOP – PW  
Reel of 2000  
Reel of 250  
Reel of 2000  
SN74LVC240APWR  
SN74LVC240APWT  
SN74LVC240ADGVR  
LC240A  
TVSOP – DGV  
LC240A  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1993–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...15

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