Datasheet > 逻辑 > 总线驱动器/收发器> SN74LVC2G126-EP

SN74LVC2G126-EP

更新时间： 2024-11-20 11:07:03

品牌	Logo	应用领域
德州仪器 - TI		驱动总线驱动器总线收发器
页数	文件大小	规格书
13页	767K
描述
具有三态输出的增强型产品 2 通道、1.65V 至 5.5V 缓冲器

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SN74LVC2G126-EP 数据手册

SN74LVC2G126-EP

www.ti.com

SCES856 –DECEMBER 2013

DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS

Check for Samples: SN74LVC2G126-EP

FEATURES

•

Supports 5-V V_CCOperation

SUPPORTS DEFENSE, AEROSPACE,

AND MEDICAL APPLICATIONS

Inputs Accept Voltages to 5.5 V

Max t_pdof 6.8 ns at 3.3 V

•

Controlled Baseline

One Assembly and Test Site

One Fabrication Site

Low Power Consumption, 10-μA Max I_CC

±24-mA Output Drive at 3.3 V

Available in Military (–55°C to 125°C)

Temperature Range

Typical V_OLP(Output Ground Bounce)

<0.8 V at V_CC= 3.3 V, T_A= 25°C

•

Extended Product Life Cycle

Extended Product-Change Notification

Product Traceability

•

Typical V_OHV(Output V_OHUndershoot)

>2 V at V_CC= 3.3 V, T_A= 25°C

I_offSupports Partial-Power-Down Mode

Operation

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

DCU PACKAGE

(TOP VIEW)

ESD Protection Exceeds JESD 22

V_CC

2OE

1OE

–

2000-V Human-Body Model (A114-A)

200-V Machine Model (A115-A)

GND

1000-V Charged-Device Model (C101)

DESCRIPTION

This dual bus buffer gate is designed for 1.65-V to 5.5-V V_CCoperation.

The SN74LVC2G126 is a dual bus driver/line driver with 3-state outputs. The outputs are disabled when the

associated output-enable (OE) input is low.

To ensure the high-impedance state during power up or power down, OE should be tied to GND through a

pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.

This device is fully specified for partial-power-down applications using I_off. The I_offcircuitry disables the outputs,

preventing damaging current backflow through the device when it is powered down.

ORDERING INFORMATION⁽¹⁾

T_J

PACKAGE⁽²⁾

ORDERABLE PART NUMBER

TOP-SIDE MARKING

VID NUMBER

–55°C to 125°C

VSSOP - DCU Tape of 250

CLVC2G126MDCUTEP

CEPR

V62/14604-01XE

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

Function Table

(Each Buffer)

INPUTS

OUTPUT

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

12 3 4 5 6 7...13

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与SN74LVC2G126-EP相关器件

型号	品牌	获取价格	描述	数据表
SN74LVC2G126YEAR	TI	获取价格	DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS
SN74LVC2G126YEPR	TI	获取价格	DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS
SN74LVC2G126YZAR	TI	获取价格	DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS
SN74LVC2G126YZPR	TI	获取价格	DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS
SN74LVC2G132	TI	获取价格	DUAL 2-INPUT NAND GATE WITH SCHMITT-TRIGGER INPUTS
SN74LVC2G132_07	TI	获取价格	DUAL 2-INPUT NAND GATE WITH SCHMITT-TRIGGER INPUTS
SN74LVC2G132_16	TI	获取价格	Dual 2-Input NAND Gate With Schmitt-Trigger Inputs
SN74LVC2G132DCTR	TI	获取价格	DUAL 2-INPUT NAND GATE WITH SCHMITT-TRIGGER INPUTS
SN74LVC2G132DCUR	TI	获取价格	DUAL 2-INPUT NAND GATE WITH SCHMITT-TRIGGER INPUTS
SN74LVC2G132DCUT	TI	获取价格	DUAL 2-INPUT NAND GATE WITH SCHMITT-TRIGGER INPUTS

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