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SN74LVC2G132_07 PDF预览

SN74LVC2G132_07

更新时间: 2024-11-23 05:29:31
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德州仪器 - TI 触发器输入元件
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描述
DUAL 2-INPUT NAND GATE WITH SCHMITT-TRIGGER INPUTS

SN74LVC2G132_07 数据手册

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SN74LVC2G132  
DUAL 2-INPUT NAND GATE  
WITH SCHMITT-TRIGGER INPUTS  
www.ti.com  
SCES547CFEBRUARY 2004REVISED JANUARY 2007  
FEATURES  
Available in Texas Instruments NanoFree™  
Package  
Ioff Supports Partial-Power-Down Mode  
Operation  
Supports 5-V VCC Operation  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
Inputs Accept Voltages to 5.5 V  
Max tpd of 5.3 ns at 3.3 V  
ESD Protection Exceeds JESD 22  
2000-V Human-Body Model (A114-A)  
200-V Machine Model (A115-A)  
Low Power Consumption, 10-µA Max ICC  
±24-mA Output Drive at 3.3 V  
1000-V Charged-Device Model (C101)  
Typical VOLP (Output Ground Bounce) <0.8 V  
at VCC = 3.3 V, TA = 25°C  
Typical VOHV (Output VOH Undershoot) >2 V at  
VCC = 3.3 V, TA = 25°C  
DCT PACKAGE  
(TOP VIEW)  
DCU PACKAGE  
(TOP VIEW)  
YZP PACKAGE  
(BOTTOM VIEW)  
4 5  
GND  
2Y  
2A  
2B  
VCC  
1Y  
2B  
2A  
1
2
3
4
8
7
6
5
1A  
1B  
VCC  
1Y  
2B  
2A  
1
2
3
4
8
7
6
5
1A  
1B  
3 6  
2 7  
1 8  
1B  
1Y  
2Y  
VCC  
1A  
GND  
2Y  
GND  
See mechanical drawings for dimensions.  
DESCRIPTION/ORDERING INFORMATION  
This dual 2-input NAND gate with Schmitt-trigger inputs is designed for 1.65-V to 5.5-V VCC operation.  
The SN74LVC2G132 contains two inverters and performs the Boolean function Y = A B or Y = A + B in positive  
logic. The device functions as two independent inverters, but because of Schmitt action, it has different input  
threshold levels for positive-going (VT+) and negative-going (VT-) signals.  
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the  
package.  
This device can be triggered from the slowest of input ramps and still give clean jitter-free output signals.  
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,  
preventing damaging current backflow through the device when it is powered down.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
TOP-SIDE MARKING(2)  
_ _ _D5_  
NanoFree™ – WCSP (DSBGA)  
0.23-mm Large Bump – YZP (Pb-free)  
Reel of 3000 SN74LVC2G132YZPR  
SSOP – DCT  
Reel of 3000 SN74LVC2G132DCTR  
Reel of 3000 SN74LVC2G132DCUR  
C3B_ _ _  
C3B_  
–40°C to 85°C  
VSSOP – DCU  
Reel of 250  
SN74LVC2G132DCUT  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
(2) DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.  
DCU: The actual top-side marking has one additional character that designates the assembly/test site.  
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following  
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, = Pb-free).  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoFree is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2004–2007, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  

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