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SN74LVC2G126DCUT PDF预览

SN74LVC2G126DCUT

更新时间： 2024-01-19 05:29:29
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器输出元件
页数 文件大小 规格书
13页 333K
描述
DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS

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中文翻译

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SN74LVC2G126DCUT 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：BGA
包装说明：GREEN, DSBGA-8针数：8
Reach Compliance Code：unknown风险等级：5.31
Is Samacsys：N系列：LVC/LCX/Z
JESD-30 代码：R-PBGA-B8JESD-609代码：e1
长度：1.9 mm逻辑集成电路类型：BUS DRIVER
湿度敏感等级：1位数：1
功能数量：2端口数量：2
端子数量：8最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：VFBGA封装形状：RECTANGULAR
封装形式：GRID ARRAY, VERY THIN PROFILE, FINE PITCH峰值回流温度（摄氏度）：260
传播延迟（tpd）：9.8 ns座面最大高度：0.5 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：1.65 V
标称供电电压 (Vsup)：1.8 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：TIN SILVER COPPER端子形式：BALL
端子节距：0.5 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：0.9 mm
Base Number Matches：1

SN74LVC2G126DCUT 数据手册

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SCES205H − APRIL 1999 − REVISED SEPTEMBER 2003  
DCT OR DCU PACKAGE  
(TOP VIEW)  
D
Available in the Texas Instruments  
NanoStarand NanoFreePackages  
D
D
D
D
D
D
Supports 5-V V  
Operation  
CC  
1OE  
1A  
2Y  
V
CC  
2OE  
1Y  
2A  
1
2
3
4
8
7
6
5
Inputs Accept Voltages to 5.5 V  
Max t of 4 ns at 3.3 V  
pd  
Low Power Consumption, 10-µA Max I  
GND  
CC  
24-mA Output Drive at 3.3 V  
YEA, YEP, YZA, OR YZP PACKAGE  
(BOTTOM VIEW)  
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
= 3.3 V, T = 25°C  
OLP  
CC  
A
D
D
D
D
Typical V  
(Output V  
Undershoot)  
4 5  
3 6  
2 7  
1 8  
GND  
2Y  
1A  
2A  
1Y  
2OE  
OHV  
OH  
>2 V at V  
= 3.3 V, T = 25°C  
CC  
A
I
Supports Partial-Power-Down Mode  
off  
1OE  
V
Operation  
CC  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
− 1000-V Charged-Device Model (C101)  
description/ordering information  
This dual bus buffer gate is designed for 1.65-V to 5.5-V V  
operation.  
CC  
NanoStarand NanoFreepackage technology is a major breakthrough in IC packaging concepts, using the  
die as the package.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
T
A
PACKAGE  
‡
NanoStar− WCSP (DSBGA)  
0.17-mm Small Bump − YEA  
SN74LVC2G126YEAR  
SN74LVC2G126YZAR  
SN74LVC2G126YEPR  
SN74LVC2G126YZPR  
NanoFree− WCSP (DSBGA)  
0.17-mm Small Bump − YZA (Pb-free)  
Reel of 3000  
_ _ _CN_  
NanoStar− WCSP (DSBGA)  
0.23-mm Large Bump − YEP  
−40°C to 85°C  
NanoFree− WCSP (DSBGA)  
0.23-mm Large Bump − YZP (Pb-free)  
SSOP − DCT  
Reel of 3000  
Reel of 3000  
SN74LVC2G126DCTR  
SN74LVC2G126DCUR  
C26_ _ _  
C26_  
VSSOP − DCU  
Reel of 250  
SN74LVC2G126DCUT  
†
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.  
DCU: The actual top-side marking has one additional character that designates the assembly/test site.  
YEA/YZA,YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code,  
and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition  
(1 = SnPb, • = Pb-free).  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoStar and NanoFree are trademarks of Texas Instruments.  
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Copyright 2003, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...13

中文翻译

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SN74LVC2G126DCUT 替代型号

型号 品牌 替代类型 描述 数据表
74LVC2G126DCUTG4 TI

完全替代

 DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS
CLVC2G126MDCUTEP TI

类似代替

 DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS
SN74LVC2G126DCUR TI

类似代替

 DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS

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