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SCES205H − APRIL 1999 − REVISED SEPTEMBER 2003
DCT OR DCU PACKAGE
(TOP VIEW)
D
Available in the Texas Instruments
NanoStar and NanoFree Packages
D
D
D
D
D
D
Supports 5-V V
Operation
CC
1OE
1A
2Y
V
CC
2OE
1Y
2A
1
2
3
4
8
7
6
5
Inputs Accept Voltages to 5.5 V
Max t of 4 ns at 3.3 V
pd
Low Power Consumption, 10-µA Max I
GND
CC
24-mA Output Drive at 3.3 V
YEA, YEP, YZA, OR YZP PACKAGE
(BOTTOM VIEW)
Typical V
<0.8 V at V
(Output Ground Bounce)
= 3.3 V, T = 25°C
OLP
CC
A
D
D
D
D
Typical V
(Output V
Undershoot)
4 5
3 6
2 7
1 8
GND
2Y
1A
2A
1Y
2OE
OHV
OH
>2 V at V
= 3.3 V, T = 25°C
CC
A
I
Supports Partial-Power-Down Mode
off
1OE
V
Operation
CC
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
description/ordering information
This dual bus buffer gate is designed for 1.65-V to 5.5-V V
operation.
CC
NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
T
A
PACKAGE
‡
NanoStar − WCSP (DSBGA)
0.17-mm Small Bump − YEA
SN74LVC2G126YEAR
SN74LVC2G126YZAR
SN74LVC2G126YEPR
SN74LVC2G126YZPR
NanoFree − WCSP (DSBGA)
0.17-mm Small Bump − YZA (Pb-free)
Reel of 3000
_ _ _CN_
NanoStar − WCSP (DSBGA)
0.23-mm Large Bump − YEP
−40°C to 85°C
NanoFree − WCSP (DSBGA)
0.23-mm Large Bump − YZP (Pb-free)
SSOP − DCT
Reel of 3000
Reel of 3000
SN74LVC2G126DCTR
SN74LVC2G126DCUR
C26_ _ _
C26_
VSSOP − DCU
Reel of 250
SN74LVC2G126DCUT
†
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.
DCU: The actual top-side marking has one additional character that designates the assembly/test site.
YEA/YZA,YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code,
and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition
(1 = SnPb, • = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar and NanoFree are trademarks of Texas Instruments.
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Copyright 2003, Texas Instruments Incorporated
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