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SN74AUC2G126YEPR PDF预览

SN74AUC2G126YEPR

更新时间： 2024-11-16 05:17:39
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器逻辑集成电路输出元件
页数 文件大小 规格书
12页 258K
描述
DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS

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中文翻译

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SN74AUC2G126YEPR 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：BGA包装说明：VFBGA, BGA8,2X4,20
针数：8Reach Compliance Code：not_compliant
风险等级：5.8控制类型：ENABLE HIGH
系列：AUCJESD-30 代码：R-PBGA-B8
长度：1.9 mm负载电容（CL）：15 pF
逻辑集成电路类型：BUS DRIVER最大I（ol）：0.005 A
位数：1功能数量：2
端口数量：2端子数量：8
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：VFBGA
封装等效代码：BGA8,2X4,20封装形状：RECTANGULAR
封装形式：GRID ARRAY, VERY THIN PROFILE, FINE PITCH包装方法：TAPE AND REEL
峰值回流温度（摄氏度）：NOT SPECIFIED电源：1.2/2.5 V
Prop。Delay @ Nom-Sup：3.5 ns传播延迟（tpd）：3.5 ns
认证状态：Not Qualified座面最大高度：0.5 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：2.7 V
最小供电电压 (Vsup)：0.8 V标称供电电压 (Vsup)：1.2 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：BALL
端子节距：0.5 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：0.9 mm
Base Number Matches：1

SN74AUC2G126YEPR 数据手册

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SCES533A − DECEMBER 2003 − REVISED FEBRUARY 2004  
DCT OR DCU PACKAGE  
(TOP VIEW)  
D
D
Available in the Texas Instruments  
NanoStarand NanoFreePackages  
Optimized for 1.8-V Operation and Is 3.6-V  
I/O Tolerant to Support Mixed-Mode Signal  
Operation  
1
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8
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1OE  
1A  
2Y  
V
CC  
2OE  
1Y  
2A  
D
I
Supports Partial-Power-Down Mode  
off  
GND  
Operation  
D
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Sub 1-V Operable  
YEP OR YZP PACKAGE  
(BOTTOM VIEW)  
Max t of 1.9 ns at 1.8 V  
pd  
Low Power Consumption, 10 µA at 1.8 V  
4 5  
3 6  
2 7  
1 8  
GND  
2Y  
1A  
2A  
1Y  
2OE  
8-mA Output Drive at 1.8 V  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
1OE  
V
CC  
D
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
− 1000-V Charged-Device Model (C101)  
description/ordering information  
This dual bus buffer gate is operational at 0.8-V to 2.7-V V , but is designed specifically for 1.65-V to 1.95-V  
CC  
V
operation.  
CC  
The SN74AUC2G126 is a dual bus driver/line driver with 3-state outputs. The outputs are disabled when the  
associated output-enable (OE) input is low.  
NanoStarand NanoFreepackage technology is a major breakthrough in IC packaging concepts, using the  
die as the package.  
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a  
pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the  
driver.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
T
A
PACKAGE  
‡
NanoStar− WCSP (DSBGA)  
0.23-mm Large Bump − YEP  
Tape and reel SN74AUC2G126YEPR  
Tape and reel SN74AUC2G126YZPR  
_ _ _UN_  
NanoFree− WCSP (DSBGA)  
0.23-mm Large Bump − YZP (Pb-free)  
−40°C to 85°C  
SSOP − DCT  
Tape and reel SN74AUC2G126DCTR  
Tape and reel SN74AUC2G126DCUR  
U26_ _ _  
UN_  
VSSOP − DCU  
†
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.  
DCU: The actual top-side marking has one additional character that designates the assembly/test site.  
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one  
following character to designate the assembly/test site. Pin  
1 identifier indicates solder-bump composition  
(1 = SnPb, • = Pb-free).  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoStar and NanoFree are trademarks of Texas Instruments.  
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Copyright 2004, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...12

中文翻译

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