SN74AUC2G126

更新时间： 2024-11-16 05:17:39

品牌	Logo	应用领域
德州仪器 - TI		输出元件
页数	文件大小	规格书
12页	258K
描述
DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS

阅读下载

中文翻译

获取价格

数据手册
替代型号

如果您发现信息不准确，欢迎纠错

SN74AUC2G126 数据手册

ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈ ꢉꢇ ꢊ

ꢋꢅꢄ ꢌ ꢍꢅꢀ ꢍꢅꢎ ꢎꢏ ꢐ ꢈ ꢄꢑꢏ

ꢒ ꢓꢑ ꢔ ꢕ ꢖꢀꢑꢄꢑ ꢏ ꢗ ꢅꢑ ꢘ ꢅꢑꢀ

SCES533A − DECEMBER 2003 − REVISED FEBRUARY 2004

DCT OR DCU PACKAGE

(TOP VIEW)

Available in the Texas Instruments

NanoStar and NanoFree Packages

Optimized for 1.8-V Operation and Is 3.6-V

I/O Tolerant to Support Mixed-Mode Signal

Operation

1OE

2OE

Supports Partial-Power-Down Mode

off

GND

Operation

Sub 1-V Operable

YEP OR YZP PACKAGE

(BOTTOM VIEW)

Max t of 1.9 ns at 1.8 V

Low Power Consumption, 10 µA at 1.8 V

4 5

3 6

2 7

1 8

GND

2OE

8-mA Output Drive at 1.8 V

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

1OE

ESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

− 1000-V Charged-Device Model (C101)

description/ordering information

This dual bus buffer gate is operational at 0.8-V to 2.7-V V , but is designed specifically for 1.65-V to 1.95-V

operation.

The SN74AUC2G126 is a dual bus driver/line driver with 3-state outputs. The outputs are disabled when the

associated output-enable (OE) input is low.

NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the

die as the package.

To ensure the high-impedance state during power up or power down, OE should be tied to GND through a

pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the

driver.

ORDERING INFORMATION

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

†

PACKAGE

‡

NanoStar − WCSP (DSBGA)

0.23-mm Large Bump − YEP

Tape and reel SN74AUC2G126YEPR

Tape and reel SN74AUC2G126YZPR

_ _ _UN_

NanoFree − WCSP (DSBGA)

0.23-mm Large Bump − YZP (Pb-free)

−40°C to 85°C

SSOP − DCT

Tape and reel SN74AUC2G126DCTR

Tape and reel SN74AUC2G126DCUR

U26_ _ _

UN_

VSSOP − DCU

†

‡

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.

DCU: The actual top-side marking has one additional character that designates the assembly/test site.

YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one

following character to designate the assembly/test site. Pin

1 identifier indicates solder-bump composition

^{(1 = SnPb,}• = Pb-free).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

NanoStar and NanoFree are trademarks of Texas Instruments.

ꢘ

ꢐ

ꢗ

ꢨ

ꢋ

ꢣ

ꢅ

ꢆ

ꢡ

ꢑ

ꢢ

ꢓ

ꢜ

ꢗ

ꢚ

ꢁ

ꢛ

ꢋ

ꢄ

ꢑ

ꢄ

ꢙ

ꢚ

ꢤ

ꢛ

ꢜ

ꢢ

ꢝ

ꢞ

ꢟ

ꢠ

ꢙ

ꢜ

ꢚ

ꢙ

ꢡ

ꢥ

ꢢ

ꢣ

ꢝ

ꢤ

ꢚ

ꢠ

ꢟ

ꢞ

ꢡ

ꢜ

ꢛ

ꢥ

ꢑꢤ

ꢣ

ꢦ

ꢡ

ꢧ

ꢙ

ꢢ

ꢟ

ꢡ

ꢠ

ꢙ

ꢠ

ꢜ

ꢝ

ꢚ

ꢣ

ꢨ

ꢟ

ꢚ

ꢠ

ꢤ

ꢡ

ꢩ

ꢝ

ꢜ

ꢢ

ꢠ

ꢜ

ꢝ

ꢞ

ꢠ

ꢜ

ꢡ

ꢥ

ꢙ

ꢛ

ꢙ

ꢢ

ꢤ

ꢝ

ꢠ

ꢪ

ꢠ

ꢤ

ꢝ

ꢜ

ꢛ

ꢫ

ꢟ

ꢓ

ꢚ

ꢞ

ꢤ

ꢡ

ꢠ

ꢟ

ꢚ

ꢨ

ꢟ

ꢝ

ꢨ

ꢬ

ꢟ

ꢠ ꢤ ꢡ ꢠꢙ ꢚꢮ ꢜꢛ ꢟ ꢧꢧ ꢥꢟ ꢝ ꢟ ꢞ ꢤ ꢠ ꢤ ꢝ ꢡ ꢩ

ꢝ

ꢟ

ꢚ

ꢠ

ꢭ

ꢩ

ꢘ

ꢝ

ꢜ

ꢨ

ꢣ

ꢢ

ꢠ

ꢙ

ꢜ

ꢚ

ꢥ

ꢝ

ꢜ

ꢢ

ꢤ

ꢡ

ꢙ

ꢚ

ꢮ

ꢨ

ꢜ

ꢤ

ꢡ

ꢚ

ꢜ

ꢠ

ꢚ

ꢤ

ꢢ

ꢤ

ꢡ

ꢟ

ꢝ

ꢙ

ꢧ

ꢭ

ꢙ

ꢚ

ꢢ

ꢧ

ꢣ

ꢨ

ꢤ

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...12

中文翻译

下载PDF

SN74AUC2G126 替代型号

型号	品牌	替代类型	描述	数据表
SN74AUP2G126	TI	功能相似	LOW-POWER DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS

与SN74AUC2G126相关器件

型号	品牌	获取价格	描述	数据表
SN74AUC2G126_08	TI	获取价格	DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS
SN74AUC2G126DCTR	TI	获取价格	DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS
SN74AUC2G126DCUR	TI	获取价格	DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS
SN74AUC2G126YEPR	TI	获取价格	DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS
SN74AUC2G126YZPR	TI	获取价格	DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS
SN74AUC2G240	TI	获取价格	DUAL BUFFER/DRIVER WITH 3-STATE OUTPUTS
SN74AUC2G240DCTR	TI	获取价格	DUAL BUFFER/DRIVER WITH 3-STATE OUTPUTS
SN74AUC2G240DCUR	TI	获取价格	DUAL BUFFER/DRIVER WITH 3-STATE OUTPUTS
SN74AUC2G240DCURE4	TI	获取价格	IC,BUFFER/DRIVER,SINGLE,2-BIT,AUC-CMOS,TSSOP,8PIN,PLASTIC
SN74AUC2G240YEPR	TI	获取价格	AUC SERIES, 1-BIT DRIVER, INVERTED OUTPUT, PBGA8, DSBGA-8

与SN74AUC2G126相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

13
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

7
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

35
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

31

产品中心

服务支持

精选活动

关于我们

帮助中心

SN74AUC2G126

SN74AUC2G126 数据手册

SN74AUC2G126 替代型号

与SN74AUC2G126相关器件

与SN74AUC2G126相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

SN74AUC2G126

SN74AUC2G126 数据手册

SN74AUC2G126 替代型号

与SN74AUC2G126相关器件

与SN74AUC2G126相关文章

您还可以找

您在本页遇到什么问题？