Datasheet > SN65LVDS302_07

SN65LVDS302_07

更新时间： 2024-11-06 05:25:03

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德州仪器 - TI		/
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描述
PROGRAMMABLE 27-BIT SERIAL-TO-PARALLEL RECEIVER

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SN65LVDS302_07 数据手册

SN65LVDS302

www.ti.com

SLLS733B–JUNE 2006–REVISED FEBRUARY 2007

PROGRAMMABLE 27-BIT SERIAL-TO-PARALLEL RECEIVER

The serial data and clock are received via Sub

Low-Voltage Differential Signalling (SubLVDS) lines.

The SN65LVDS302 supports three operating power

modes (Shutdown, Standby, and Active) to conserve

power.

FEATURES

•

Serial Interface Technology

•

Compatible with FlatLink™3G such as

SN65LVDS301

•

Supports Video Interfaces up to 24-bit RGB

Data and 3 Control Bits Received over 1, 2 or

3 SubLVDS Differential Lines

When receiving, the PLL locks to the incoming clock

CLK and generates an internal high-speed clock at

the line rate of the data lines. The data is serially

loaded into

a shift register using the internal

•

SubLVDS Differential Voltage Levels

Up to 1.755 Gbps Data Throughput

Three Operating Modes to Conserve Power

high-speed clock. The deserialized data is presented

on the parallel output bus with a recreation of the

Pixel clock PCLK generated from the internal

high-speed clock. If no input CLK signal is present,

the output bus is held static with the PCLK and DE

held low, while all other parallel outputs are pulled

high.

–

Active mode QVGA - 17 mW

Typical Shutdown - 0.7 µW

Typical Standby Mode - 27 µW Typical

•

Bus-Swap Function for PCB-Layout Flexibility

ESD Rating > 4 kV (HBM)

The parallel (CMOS) output bus offers a bus-swap

feature. The SWAP control pin controls the output

pin order of the output pixel data to be either R[7:0].

G[7:0], B[7:0], VS, HS, DE or B[0:7], G[0:7], R[0:7],

VS, HS, DE. This gives a PCB designer the flexibility

to better match the bus to the LCD driver pinout or to

put the receiver device on the top side or the bottom

side of the PCB. The F/S control input selects

between a slow CMOS bus output rise time for best

EMI and power consumption and a fast CMOS

output for increased speed or higher load designs.

Pixel Clock Range of 4 MHz–65 MHz

Failsafe on all CMOS Inputs

Packaged in 5 mm x 5 mm MicroStar Junior

µBGA^®with 0,5 mm Ball Pitch

•

Very low EMI meets SAE J1752/3 'Kh'-spec

APPLICATIONS

•

Small Low-Emission Interface between

Graphics Controller and LCD Display

•

Mobile Phones & Smart Phones

Portable Multimedia Players

LCD

Driver

Flatlinkä3G

DESCRIPTION

The

SN65LVDS302

receiver

de-serializes

LVDS302

CLK DATA

LVDS301

FlatLink™3G compliant serial input data to 27

parallel data outputs. The SN65LVDS302 receiver

contains one shift register to load 30 bits from 1, 2 or

3 serial inputs and latches the 24 pixel bits and 3

control bits out to the parallel CMOS outputs after

checking the parity bit. If the parity check confirms

correct parity, the Channel Parity Error (CPE) output

remains low. If a parity error is detected, the CPE

output generates a high pulse while the data output

bus disregards the newly-received pixel. Instead, the

last data word is held on the output bus for another

clock cycle.

Application

Processor

with

RGB

Video

Interface

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

FlatLink is a trademark of Texas Instruments.

µBGA is a registered trademark of Tessera, Inc.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

12 3 4 5 6 7...41

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与SN65LVDS302_07相关器件

型号	品牌	获取价格	描述	数据表
SN65LVDS302_V01	TI	获取价格	SN65LVDS302 Programmable 27-Bit Serial-to-Parallel Receiver
SN65LVDS302ZQE	TI	获取价格	PROGRAMMABLE 27-BIT SERIAL-TO-PARALLEL RECEIVER
SN65LVDS302ZQER	TI	获取价格	PROGRAMMABLE 27-BIT SERIAL-TO-PARALLEL RECEIVER
SN65LVDS302ZXH	TI	获取价格	SN65LVDS302 Programmable 27-Bit Serial-to-Parallel Receiver
SN65LVDS302ZXHR	TI	获取价格	SN65LVDS302 Programmable 27-Bit Serial-to-Parallel Receiver
SN65LVDS303	TI	获取价格	PROGRAMMABLE 27-BIT DISPLAY SERIAL-INTERFACE TRANSMITTER
SN65LVDS303ZQE	TI	获取价格	LINE DRIVER, PBGA80, 5 X 5 MM, PLASTIC, MICRO, BGA-80
SN65LVDS303ZQER	TI	获取价格	PROGRAMMABLE 27-BIT DISPLAY SERIAL-INTERFACE TRANSMITTER
SN65LVDS304	TI	获取价格	PROGRAMMABLE 27-BIT PARALLEL-TO-SERIAL RECEIVER
SN65LVDS304ZQER	TI	获取价格	PROGRAMMABLE 27-BIT PARALLEL-TO-SERIAL RECEIVER

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