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SN65LVDS310ZQCT PDF预览

SN65LVDS310ZQCT

更新时间： 2024-11-06 11:58:19
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
32页 1435K
描述
PROGRAMMABLE 27-BIT SERIAL-TO-PARALLEL RECEIVER

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SN65LVDS310ZQCT 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：BGA
包装说明：VFBGA, BGA48,7X7,20针数：48
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：5.81差分输出：NO
高电平输入电流最大值：0.00002 A输入特性：DIFFERENTIAL
接口集成电路类型：LINE RECEIVERJESD-30 代码：S-PBGA-B48
JESD-609代码：e1长度：4 mm
湿度敏感等级：3功能数量：1
端子数量：48最高工作温度：85 °C
最低工作温度：-40 °C最大输出低电流：0.39 A
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：VFBGA封装等效代码：BGA48,7X7,20
封装形状：SQUARE封装形式：GRID ARRAY, VERY THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）：260电源：1.8 V
认证状态：Not Qualified最大接收延迟：2.5 ns
接收器位数：27座面最大高度：1 mm
子类别：Line Driver or Receivers最大压摆率：25 mA
最大供电电压：1.95 V最小供电电压：1.65 V
标称供电电压：1.8 V电源电压1-最大：1.95 V
电源电压1-分钟：1.65 V电源电压1-Nom：1.8 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：BALL端子节距：0.5 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：4 mm

SN65LVDS310ZQCT 数据手册

 浏览型号SN65LVDS310ZQCT的Datasheet PDF文件第2页浏览型号SN65LVDS310ZQCT的Datasheet PDF文件第3页浏览型号SN65LVDS310ZQCT的Datasheet PDF文件第4页浏览型号SN65LVDS310ZQCT的Datasheet PDF文件第5页浏览型号SN65LVDS310ZQCT的Datasheet PDF文件第6页浏览型号SN65LVDS310ZQCT的Datasheet PDF文件第7页 
SN65LVDS310  
www.ti.com  
SLLS836–MAY 2007  
PROGRAMMABLE 27-BIT SERIAL-TO-PARALLEL RECEIVER  
When receiving, the PLL locks to the incoming clock,  
CLK, and generates an internal high-speed clock at  
the line rate of the data lines. The data is serially  
FEATURES  
•
Serial Interface Technology  
•
Compatible With FlatLink™ 3G Transmitters  
(E.g., SN65LVDS305 or SN65LVDS307)  
loaded into  
a shift register using the internal  
high-speed clock. The deserialized data is presented  
on the parallel output bus with a recreation of the  
pixel clock, PCLK, generated from the internal  
high-speed clock. If no input CLK signal is present,  
the output bus is held static with PCLK and DE held  
low, while all other parallel outputs are pulled high.  
•
Supports Video Interfaces up to 24-Bit RGB  
Data and 3 Control Bits Received Over One  
SubLVDS Differential Data Line  
•
•
•
SubLVDS Differential Voltage Levels  
Up to 405-Mbps Data Throughput  
The F/S conrol input selects between a slow CMOS  
bus output rise time for best EMI and power  
consumption and a fast CMOS output for increased  
speed or higher-load designs.  
Three Operating Modes to Conserve Power  
–
–
–
Active mode QVGA: 17 mW  
Typical Shutdown: 0.7 µW  
Typical Standby Mode: 67 µW Typical  
•
•
•
•
ESD Rating > 4 kV (HBM)  
Pixel-Clock Range of 4 MHz–15 MHz  
Failsafe on All CMOS Inputs  
Packaged in 4-mm × 4-mm MicroStar  
Junior™µBGA® With 0,5-mm Ball Pitch  
LCD  
Driver  
Flatlinkä3G  
•
Very Low EMI  
APPLICATIONS  
LVDS310  
CLK DATA  
LVDS307  
•
Small Low-Emission Interface Between  
Graphics Controller and LCD Display  
•
•
Mobile Phones and Smart Phones  
Portable Multimedia Players  
DESCRIPTION  
The SN65LVDS310 receiver deserializes FlatLink  
3G-compliant serial input data to 27 parallel data  
outputs. The SN65LVDS310 receiver contains one  
shift register to load 30 bits from one serial input and  
latches the 24 pixel bits and 3 control bits out to the  
parallel CMOS outputs after checking the parity bit. If  
a parity error is detected, the data output bus  
disregards the newly received pixel. Instead, the last  
data word is held on the output bus for another clock  
cycle.  
Application  
Processor  
with  
1
4
7
3
6
9
#
2
5
8
0
RGB  
Video  
Interface  
*
M0056-04  
The serial data and clock are received via  
sub-low-voltage differential signalling (SubLVDS)  
lines. The SN65LVDS310 supports three operating  
power modes (shutdown, standby, and active) to  
conserve power.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
FlatLink, MicroStar Junior are trademarks of Texas Instruments.  
µBGA is a registered trademark of Tessera, Inc.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2007, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...32

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SN65LVDS310ZQCT 替代型号

型号 品牌 替代类型 描述 数据表
SN65LVDS310ZQCR TI

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