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SN65LVDS315 PDF预览

SN65LVDS315

更新时间: 2024-09-16 05:25:03
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德州仪器 - TI 转换器
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34页 1983K
描述
CAMERA PARALLEL RGB TO MIPI CSI-1 SERIAL CONVERTER

SN65LVDS315 数据手册

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SN65LVDS315  
www.ti.com  
SLLS881ADECEMBER 2007REVISED MARCH 2008  
CAMERA PARALLEL RGB TO MIPI CSI-1 SERIAL CONVERTER  
The serialized data is presented on the differential  
serial data output DOUT with a differential clock  
signal on output CLK. The frequency of CLK is 8× the  
DCLK input pixel clock rate.  
1
FEATURES  
MIPI CSI-1 and SMIA CCP Support  
Connects Directly to OMAP CSI Interface  
4×4 mm QFN Package  
Flexible printed circuit (FPC) cabling typically  
interconnects the SN65LVDS315 with the CSI-1  
compliant receiver. Compared to parallel signalling,  
the SN65LVDS315 outputs significantly reduce the  
EMI of the interconnect.  
ESD Rating >3 kV (HBM) Camera Input Ports  
and >2 kV (HBM) All Other Ports  
Pixel Clock Range 3.5–26 MHz  
Three Operating Modes to Conserve Power  
The SN65LVDS315 supports three power modes  
(shutdown, standby and active) to conserve power.  
The TXEN input may be used to put the  
Active Mode VGA Camera 30 fps: 7 mA  
Typical Shutdown and Standby: 0.5 µA  
EMI  
SN65LVDS315 in  
a
shutdown mode. The  
SN65LVDS315 enters an active standby mode if the  
input clock, DCLK, stops. This minimizes power  
consumption without the need for controlling an  
external terminal.  
APPLICATIONS  
Camera to Host Controller (e.g. OMAP2420,  
OMAP2430, OMAP3430)  
The SN65LVDS315 is characterized for operation  
over ambient air temperatures of –40°C to 85°C. All  
CMOS inputs offer failsafe operation to protect the  
input from damage during power up and to avoid  
current flow into the device inputs during power up.  
The core supply of the SN65LVDS315 is 1.8 V. To  
provide greater flexibility, the camera data inputs  
support a supply range from 1.8 V to 3.3 V.  
Mobile Phones and Smart Phones  
DESCRIPTION  
The SN65LVDS315 is a camera serializer that  
converts 8-bit parallel camera data into MIPI-CSI1 or  
SMIA CCP compliant serial signals.  
The device converts the parallel 8-bit data to two  
sub-low-voltage differential signaling (SubLVDS)  
serial data and clock output. The parallel data is  
latched in with the pixel clock input DCLK on the  
falling clock edge. The control inputs VS and HS are  
used to determine line and frame synchronization.  
Camera  
RGB IF  
LVDS315  
FPC  
Application  
processor  
with  
integrated  
MIPI CSI-1  
receiver  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2007–2008, Texas Instruments Incorporated  

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