Datasheet > SN65LVDS324

SN65LVDS324

更新时间： 2024-11-20 12:25:11

品牌	Logo	应用领域
德州仪器 - TI		传感器图像传感器
页数	文件大小	规格书
24页	1075K
描述
1080p60 IMAGE SENSOR RECEIVER

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SN65LVDS324 数据手册

SN65LVDS324

www.ti.com

SLLSED9 –NOVEMBER 2012

1080p60 IMAGE SENSOR RECEIVER

Check for Samples: SN65LVDS324

FEATURES

•

Low Power 1.8V CMOS Process

Configurable Output Conventions

Packaged in 4.5 x 7mm BGA

•

Bridges the Interface Between Video Image

Sensors and Processors

•

Receives Aptina HiSPi™, Panasonic LVDS, or

Sony LVDS Parallel; Outputs 1.8V CMOS with

10/12/14/16 Bits at 18.5MHz to 162MHz

APPLICATIONS

•

IP Network Cameras

Machine Vision

•

SubLVDS Inputs Support Up To 648Mbps

Integrated 100Ω Differential Input Termination

Test Image Generation Feature

Video Conferencing

Gesture Recognition

Compatible with TI OMAP™ and DaVinci™

Including DM385, DM8127, DM36x, and DMVA

DESCRIPTION

The SN65LVDS324 is a SubLVDS deserializer that recovers words, detects sync codes, multiplies the input DDR

clock by a ratio, and outputs parallel CMOS 1.8V data on the rising clock edge. It bridges the video stream

interface between HD image sensors made by leading manufacturers, to a format that common processors can

accept. The supported pixel frequency is 18.5MHz to 162MHz — suitable for resolutions from VGA to 1080p60.

Four high-level modes are supported: Aptina 1-Channel 4-Lane, Aptina 1-Channel 2-Lane, Panasonic 2-Channel

2-Port, and Sony LVDS Parallel. Each supports 10/12/14/16 bit sub-modes, according to Table 1. Each mode

also has a configurable allowable frequency range, as specified by Table 3 register PLL_CFG.

The SN65LVDS324 is configured through its I²C-programmable registers. This volatile memory must be written

after power up. Configuration options include the MSB/LSB output order, sync polarity convention, data slew

rate, and two output timing modes (long-setup or clock-centered), for wider compatibility with different processors

and software. The TESTMODE_VIDEO feature is designed to assist engineering development. The max

allowable frame size is 8191 x 8191.

With integrated differential input termination, and a footprint of 4.5 x 7mm, the SN65LVDS324 provides a

differentiated solution with optimized form, function, and cost. It operates through an ambient temperature range

of –40°C to 85°C.

spacer

Figure 1. General System Diagram

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

OMAP, DaVinci are trademarks of Texas Instruments.

HiSPi is a trademark of Aptina.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

12 3 4 5 6 7...24

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SN65LVDS324 替代型号

型号	品牌	替代类型	描述	数据表
SN65LVDS315	TI	功能相似	CAMERA PARALLEL RGB TO MIPI CSI-1 SERIAL CONVERTER

与SN65LVDS324相关器件

型号	品牌	获取价格	描述	数据表
SN65LVDS324ZQLR	TI	获取价格	1080p60 IMAGE SENSOR RECEIVER
SN65LVDS32A	TI	获取价格	HIGH-SPEED DIFFERENTIAL RECEIVERS
SN65LVDS32A_1	TI	获取价格	HIGH-SPEED DIFFERENTIAL RECEIVERS
SN65LVDS32AD	TI	获取价格	HIGH-SPEED DIFFERENTIAL RECEIVERS
SN65LVDS32AD	ROCHESTER	获取价格	QUAD LINE RECEIVER, PDSO16, PLASTIC, SO-16
SN65LVDS32ADR	TI	获取价格	High-Speed Differential Receivers 16-SOIC -40 to 85
SN65LVDS32ADR	ROCHESTER	获取价格	QUAD LINE RECEIVER, PDSO16, PLASTIC, SO-16
SN65LVDS32B	TI	获取价格	HIGH-SPEED DIFFERENTIAL RECEIVERS
SN65LVDS32B_07	TI	获取价格	HIGH-SPEED DIFFERENTIAL RECEIVERS
SN65LVDS32BD	TI	获取价格	HIGH-SPEED DIFFERENTIAL RECEIVERS

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