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SN65LVDS32ADR PDF预览

SN65LVDS32ADR

更新时间： 2024-01-05 19:05:41
品牌 Logo 应用领域
德州仪器 - TI 光电二极管接口集成电路
页数 文件大小 规格书
15页 223K
描述
High-Speed Differential Receivers 16-SOIC -40 to 85

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SN65LVDS32ADR 技术参数

是否无铅： 含铅生命周期：Active
零件包装代码：SOIC包装说明：PLASTIC, SO-16
针数：16Reach Compliance Code：unknown
风险等级：5.07差分输出：YES
输入特性：DIFFERENTIAL SCHMITT TRIGGER接口集成电路类型：LINE RECEIVER
接口标准：EIA-644; TIA-644JESD-30 代码：R-PDSO-G16
JESD-609代码：e0长度：9.9 mm
湿度敏感等级：NOT SPECIFIED功能数量：4
端子数量：16最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：NOT SPECIFIED
认证状态：COMMERCIAL最大接收延迟：6 ns
接收器位数：4座面最大高度：1.75 mm
最大供电电压：3.6 V最小供电电压：3 V
标称供电电压：3.3 V表面贴装：YES
温度等级：INDUSTRIAL端子面层：TIN LEAD
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：3.9 mmBase Number Matches：1

SN65LVDS32ADR 数据手册

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SLLS368E − JULY 1999 − REVISED JUNE 2001  
D
Meets or Exceeds the Requirements of  
NOT RECOMMENDED FOR NEW DESIGNS  
ANSI EIA/TIA-644 Standard for Signaling  
For Replacement Use SN65LVDS32B or SN65LVDT32B  
†
Rates up to 400 Mbps  
SN65LVDS32A, SN65LVDT32A  
Logic Diagram  
D
D
Operates With a Single 3.3-V Supply  
−2-V to 4.4-V Common-Mode Input Voltage  
Range  
(positive logic)  
G
D
Differential Input Thresholds <50 mV With  
50 mV of Hysteresis Over Entire  
Common-Mode Input Voltage Range  
G
D PACKAGE  
SN65LVDT32A  
(TOP VIEW)  
ONLY (4 Places)  
1A  
1Y  
D
D
D
Integrated 110-Ω Line Termination  
1B  
1A  
V
CC  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
1B  
Resistors Offered With the LVDT Series  
4B  
4A  
4Y  
G
Propagation Delay Times 4 ns (typ)  
1Y  
2A  
2B  
2Y  
3Y  
4Y  
G
Active Fail Safe Assures a High-Level  
Output With No Input  
2Y  
3A  
3B  
4A  
4B  
2A  
11 3Y  
10 3A  
D
Recommended Maximum Parallel Rate of  
100 M-Transfers/s  
2B  
GND  
9
3B  
D
Outputs High-Impedance With V  
<1.5 V  
CC  
D
Available in Small-Outline Package With  
1,27 mm Terminal Pitch  
For Replacement Use SN65LVDS3486B or SN65LVDT3486B  
SN65LVDS3486A, SN65LVDT3486A  
D
Pin-Compatible With the AM26LS32,  
MC3486, or µA9637  
D PACKAGE  
(TOP VIEW)  
Logic Diagram  
(positive logic)  
description  
SN65LVDT3486A  
1B  
1A  
V
CC  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
ONLY (4 Places)  
This family of differential line receivers offers  
improved performance and features that imple-  
ment the electrical characteristics of low-voltage  
differential signaling (LVDS). LVDS is defined in  
the TIA/EIA-644 standard. This improved perfor-  
mance represents the second generation of  
receiver products for this standard, providing a  
better overall solution for the cabled environment.  
The next generation family of products is an  
extension to TI’s overall product portfolio and is  
not necessarily a replacement for older LVDS  
receivers.  
1A  
4B  
4A  
4Y  
1Y  
1Y  
1B  
1,2EN  
1,2EN  
2Y  
2A  
2B  
12 3,4EN  
11 3Y  
2Y  
3Y  
4Y  
2A  
2B  
10 3A  
3A  
3B  
9
GND  
3B  
3,4EN  
4A  
4B  
For Replacement Use SN65LVDS9637B or SN65LVDT9637B  
SN65LVDS9637A, SN65LVDT9637A  
Improved features include an input common-  
mode voltage range 2 V wider than the minimum  
required by the standard. This will allow longer  
cable lengths by tripling the allowable ground  
noise tolerance to 3 V between a driver and  
receiver.  
D PACKAGE  
(TOP VIEW)  
Logic Diagram  
(positive logic)  
V
1A  
1B  
2A  
2B  
1
2
3
4
8
7
6
5
CC  
1Y  
1A  
1B  
1Y  
2Y  
2Y  
SN65LVDT9637A  
GND  
ONLY  
2A  
2B  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
†
Signaling rate, 1/t, where t is the minimum unit interval and is expressed in the units bits/s (bits per second)  
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Copyright 2001, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...15

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