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SN65LVDS324ZQLR PDF预览

SN65LVDS324ZQLR

更新时间： 2024-09-24 12:25:11
品牌 Logo 应用领域
德州仪器 - TI 传感器图像传感器
页数 文件大小 规格书
24页 1075K
描述
1080p60 IMAGE SENSOR RECEIVER

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SN65LVDS324ZQLR 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete包装说明：VFBGA,
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：8
模拟集成电路 - 其他类型：ANALOG CIRCUITJESD-30 代码：R-PBGA-B59
JESD-609代码：e1长度：7 mm
湿度敏感等级：3信道数量：2
功能数量：1端子数量：59
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：VFBGA
封装形状：RECTANGULAR封装形式：GRID ARRAY, VERY THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）：260座面最大高度：1 mm
最大供电电压 (Vsup)：1.95 V最小供电电压 (Vsup)：1.65 V
标称供电电压 (Vsup)：1.8 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Silver/Copper (Sn/Ag/Cu)端子形式：BALL
端子节距：0.65 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：4.5 mm
Base Number Matches：1

SN65LVDS324ZQLR 数据手册

 浏览型号SN65LVDS324ZQLR的Datasheet PDF文件第2页浏览型号SN65LVDS324ZQLR的Datasheet PDF文件第3页浏览型号SN65LVDS324ZQLR的Datasheet PDF文件第4页浏览型号SN65LVDS324ZQLR的Datasheet PDF文件第5页浏览型号SN65LVDS324ZQLR的Datasheet PDF文件第6页浏览型号SN65LVDS324ZQLR的Datasheet PDF文件第7页 
SN65LVDS324  
www.ti.com  
SLLSED9 –NOVEMBER 2012  
1080p60 IMAGE SENSOR RECEIVER  
Check for Samples: SN65LVDS324  
1
FEATURES  
•
•
•
Low Power 1.8V CMOS Process  
Configurable Output Conventions  
Packaged in 4.5 x 7mm BGA  
23  
•
Bridges the Interface Between Video Image  
Sensors and Processors  
•
Receives Aptina HiSPi™, Panasonic LVDS, or  
Sony LVDS Parallel; Outputs 1.8V CMOS with  
10/12/14/16 Bits at 18.5MHz to 162MHz  
APPLICATIONS  
•
•
•
•
IP Network Cameras  
Machine Vision  
•
•
•
•
SubLVDS Inputs Support Up To 648Mbps  
Integrated 100Ω Differential Input Termination  
Test Image Generation Feature  
Video Conferencing  
Gesture Recognition  
Compatible with TI OMAP™ and DaVinci™  
Including DM385, DM8127, DM36x, and DMVA  
DESCRIPTION  
The SN65LVDS324 is a SubLVDS deserializer that recovers words, detects sync codes, multiplies the input DDR  
clock by a ratio, and outputs parallel CMOS 1.8V data on the rising clock edge. It bridges the video stream  
interface between HD image sensors made by leading manufacturers, to a format that common processors can  
accept. The supported pixel frequency is 18.5MHz to 162MHz — suitable for resolutions from VGA to 1080p60.  
Four high-level modes are supported: Aptina 1-Channel 4-Lane, Aptina 1-Channel 2-Lane, Panasonic 2-Channel  
2-Port, and Sony LVDS Parallel. Each supports 10/12/14/16 bit sub-modes, according to Table 1. Each mode  
also has a configurable allowable frequency range, as specified by Table 3 register PLL_CFG.  
The SN65LVDS324 is configured through its I2C-programmable registers. This volatile memory must be written  
after power up. Configuration options include the MSB/LSB output order, sync polarity convention, data slew  
rate, and two output timing modes (long-setup or clock-centered), for wider compatibility with different processors  
and software. The TESTMODE_VIDEO feature is designed to assist engineering development. The max  
allowable frame size is 8191 x 8191.  
With integrated differential input termination, and a footprint of 4.5 x 7mm, the SN65LVDS324 provides a  
differentiated solution with optimized form, function, and cost. It operates through an ambient temperature range  
of –40°C to 85°C.  
spacer  
spacer  
Figure 1. General System Diagram  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
3
OMAP, DaVinci are trademarks of Texas Instruments.  
HiSPi is a trademark of Aptina.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2012, Texas Instruments Incorporated  
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