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SN65LVDS307ZQCT PDF预览

SN65LVDS307ZQCT

更新时间： 2024-11-06 03:07:59
品牌 Logo 应用领域
德州仪器 - TI 线路驱动器或接收器驱动程序和接口接口集成电路
页数 文件大小 规格书
29页 664K
描述
PROGRAMMABLE 27-BIT PARALLEL-TO-SERIAL TRANSMITTER

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中文翻译

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SN65LVDS307ZQCT 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：BGA
包装说明：VFBGA, BGA48,7X7,20针数：48
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：5.82Is Samacsys：N
差分输出：YES驱动器位数：2
输入特性：STANDARD接口集成电路类型：LINE DRIVER
接口标准：GENERAL PURPOSEJESD-30 代码：S-PBGA-B48
JESD-609代码：e1长度：4 mm
湿度敏感等级：3功能数量：1
端子数量：48最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：VFBGA封装等效代码：BGA48,7X7,20
封装形状：SQUARE封装形式：GRID ARRAY, VERY THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）：260电源：1.8 V
认证状态：Not Qualified最大接收延迟：
座面最大高度：1 mm子类别：Line Driver or Receivers
最大压摆率：25.8 mA最大供电电压：1.95 V
最小供电电压：1.65 V标称供电电压：1.8 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：BALL端子节距：0.5 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：4 mmBase Number Matches：1

SN65LVDS307ZQCT 数据手册

 浏览型号SN65LVDS307ZQCT的Datasheet PDF文件第2页浏览型号SN65LVDS307ZQCT的Datasheet PDF文件第3页浏览型号SN65LVDS307ZQCT的Datasheet PDF文件第4页浏览型号SN65LVDS307ZQCT的Datasheet PDF文件第5页浏览型号SN65LVDS307ZQCT的Datasheet PDF文件第6页浏览型号SN65LVDS307ZQCT的Datasheet PDF文件第7页 
SN65LVDS307  
www.ti.com  
SLLS834–MAY 2007  
PROGRAMMABLE 27-BIT PARALLEL-TO-SERIAL TRANSMITTER  
FPC  
cabling  
typically  
interconnects  
the  
FEATURES  
SN65LVDS307 with the display. Compared to  
parallel signaling, the SN65LVDS307 outputs  
significantly reduce the EMI of the interconnect by  
over 20 dB.  
•
FlatLink™ 3G Serial-Interface Technology  
•
Compatible With FlatLink™3G Receivers Such  
as SN65LVDS308  
•
Input Supports Video Interfaces up to 24-Bit  
RGB Data and 3 Control Bits Received Over  
Two Differential Data Lines  
The SN65LVDS307 supports three power modes  
(shutdown, standby, and active) to conserve power.  
When transmitting, the PLL locks to the incoming  
pixel clock, PCLK, and generates an internal  
high-speed clock at the line rate of the data lines.  
The parallel data are latched on the rising or falling  
edge of PCLK, as selected by the external control  
signal CPOL. The serialized data is presented on the  
serial outputs D0 and D1, together with a recreated  
PCLK that is generated from the internal high-speed  
clock and output on CLK. If PCLK stops, the device  
enters a standby mode to conserve power.  
•
•
•
SubLVDS Differential Voltage Levels  
Up to 810-Mbps Data Throughput  
Three Operating Modes to Conserve Power  
–
–
–
–
Active-Mode QVGA, 60 fps, 17.4 mW (typ)  
Active-Mode VGA, 60 fps, 28.8 mW (typ)  
Shutdown Mode ≈ 0.9 µW (typ)  
Standby Mode ≈ 0.9 µW (typ)  
•
•
•
•
•
1.8-V Supply Voltage  
ESD Rating > 3 kV (HBM)  
Pixel Clock Range of 4 MHz–30 MHz  
Failsafe on All CMOS Inputs  
4-mm × 4-mm MicroStar Junior™µBGA®  
LCD  
Driver  
Flatlinkä3G  
Package With 0,5-mm Ball Pitch  
•
Very Low EMI  
LVDS308  
CLK DATA  
LVDS307  
APPLICATIONS  
•
•
•
Host-Controller to Display-Module Interface  
Mobile Phones and Smart Phones  
Portable Multimedia Players  
Application  
Processor  
with  
1
4
7
3
6
9
#
2
5
8
0
RGB  
Video  
Interface  
DESCRIPTION  
The SN65LVDS307 serializer device converts 27  
parallel data inputs to one or two sub-low-voltage  
differential signaling (SubLVDS) serial outputs. It  
loads a shift register with 24 pixel bits and 3 control  
bits from the parallel CMOS input interface. In  
addition to the 27 data bits, the device adds a parity  
bit and two reserved bits into a 30-bit data word.  
Each word is latched into the device by the pixel  
clock (PCLK). The parity bit (odd parity) allows a  
receiver to detect single bit errors. The serial shift  
register is uploaded at 30 or 15 times the pixel-clock  
data rate, depending on the number of serial links  
used. A copy of the pixel clock is output on a  
separate differential output.  
*
M0056-03  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
FlatLink, MicroStar Junior are trademarks of Texas Instruments.  
µBGA is a registered trademark of Tessera, Inc..  
All other trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2007, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...29

中文翻译

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SN65LVDS307ZQCT 替代型号

型号 品牌 替代类型 描述 数据表
SN65LVDS307ZQCR TI

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 PROGRAMMABLE 27-BIT PARALLEL-TO-SERIAL TRANSMITTER

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