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SN65LVDS308

更新时间： 2024-11-25 05:25:03

品牌	Logo	应用领域
德州仪器 - TI		/
页数	文件大小	规格书
37页	1297K
描述
PROGRAMMABLE 27-BIT PARALLEL-TO-SERIAL RECEIVER

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SN65LVDS308 数据手册

SN65LVDS308

www.ti.com

SLLS835–MAY 2007

PROGRAMMABLE 27-BIT PARALLEL-TO-SERIAL RECEIVER

When receiving, the PLL locks to the incoming clock,

CLK, and generates an internal high-speed clock at

the line rate of the data lines. The data is serially

FEATURES

•

FlatLink 3G Serial Interface Technology

•

Compatible With FlatLink™ 3G Transmitters

Such as SN65LVDS307

loaded into

a shift register using the internal

high-speed clock. The deserialized data is presented

on the parallel output bus with a recreation of the

pixel clock, PCLK, generated from the internal

high-speed clock. If no input CLK signal is present,

the output bus is held static with PCLK and DE held

low, while all other parallel outputs are pulled high.

•

Supports Video Interfaces up to 24-Bit RGB

Data and 3 Control Bits Received Over Two

Differential Data Lines

•

SubLVDS Differential Voltage Levels

Up to 810-Mbps Data Throughput

The F/S control input selects between a slow CMOS

bus output rise time for best EMI and power

consumption and a fast CMOS output for increased

speed or higher-load designs.

Three Operating Modes to Conserve Power

–

Active mode VGA 60 fps: 17 mW

Typical Shutdown: 0.7 µW

Typical Standby Mode: 67 µW Typical

•

ESD Rating > 4 kV (HBM)

Pixel-Clock Range of 8 MHz–30 MHz

Failsafe on all CMOS Inputs

4-mm × 4-mm MicroStar Junior™µBGA^®

LCD

Driver

Flatlinkä3G

Package With 0,5-mm Ball Pitch

LVDS308

CLK DATA

LVDS307

•

Very Low EMI

APPLICATIONS

•

Small Low-Emission Interface Between

Graphics Controller and LCD Display

Application

Processor

with

•

Mobile Phones and Smart Phones

Portable Multimedia Players

RGB

Video

Interface

DESCRIPTION

The SN65LVDS308 receiver deserializes FlatLink

3G-compliant serial input data to 27 parallel data

outputs. The SN65LVDS308 receiver contains one

shift register to load 30 bits from two serial inputs

and latches the 24 pixel bits and 3 control bits out to

the parallel CMOS outputs after checking the parity

bit. If a parity error is detected, the data output bus

disregards the newly received pixel. Instead, the last

data word is held on the output bus for another clock

cycle.

M0056-03

The serial data and clock are received via

sub-low-voltage differential signalling (SubLVDS)

lines. The SN65LVDS308 supports three operating

power modes (shutdown, standby, and active) to

conserve power.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

FlatLink, MicroStar Junior are trademarks of Texas Instruments.

µBGA is a registered trademark of Tessera, Inc.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

12 3 4 5 6 7...37

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与SN65LVDS308相关器件

型号	品牌	获取价格	描述	数据表
SN65LVDS308ZQCR	TI	获取价格	PROGRAMMABLE 27-BIT PARALLEL-TO-SERIAL RECEIVER
SN65LVDS308ZQCT	TI	获取价格	PROGRAMMABLE 27-BIT PARALLEL-TO-SERIAL RECEIVER
SN65LVDS31	TI	获取价格	HIGH-SPEED DIFFERENTIAL LINE DRIVERS
SN65LVDS31_09	TI	获取价格	HIGH-SPEED DIFFERENTIAL LINE DRIVERS
SN65LVDS310	TI	获取价格	PROGRAMMABLE 27-BIT SERIAL-TO-PARALLEL RECEIVER
SN65LVDS310ZQCR	TI	获取价格	PROGRAMMABLE 27-BIT SERIAL-TO-PARALLEL RECEIVER
SN65LVDS310ZQCT	TI	获取价格	PROGRAMMABLE 27-BIT SERIAL-TO-PARALLEL RECEIVER
SN65LVDS311	TI	获取价格	可编程 27 位显示屏串行接口变送器
SN65LVDS311YFFR	TI	获取价格	可编程 27 位显示屏串行接口变送器 \| YFF \| 49 \| -40 to 85
SN65LVDS311YFFT	TI	获取价格	可编程 27 位显示屏串行接口变送器 \| YFF \| 49 \| -40 to 85

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