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SN65LVDS306ZQER

更新时间： 2024-11-27 03:40:07
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德州仪器 - TI /
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31页 1276K
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PROGRAMMABLE 27-BIT SERIAL-TO-PARALLEL RECEIVER

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SN65LVDS306ZQER 数据手册

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SN65LVDS306  
www.ti.com  
SLLS765B–SEPTEMBER 2006–REVISED FEBRUARY 2007  
PROGRAMMABLE 27-BIT SERIAL-TO-PARALLEL RECEIVER  
The serial data and clock are received via  
sub-low-voltage differential signalling (SubLVDS)  
lines. The SN65LVDS306 supports three operating  
power modes (shutdown, standby, and active) to  
conserve power.  
FEATURES  
•
Serial Interface Technology  
•
Compatible With FlatLink™3G Such as  
SN65LVDS305  
•
Supports Video Interfaces up to 24-Bit RGB  
Data and 3 Control Bits Received Over One  
SubLVDS Differential Line  
When receiving, the PLL locks to the incoming clock  
CLK and generates an internal high-speed clock at  
the line rate of the data line. The data is serially  
loaded into  
a shift register using the internal  
•
•
•
SubLVDS Differential Voltage Levels  
Up to 405-Mbps Data Throughput  
high-speed clock. The deserialized data is presented  
on the parallel output bus with a recreation of the  
pixel clock, PCLK, generated from the internal  
high-speed clock. If no input CLK signal is present,  
the output bus is held static with PCLK and DE held  
low, while all other parallel outputs are pulled high.  
Three Operating Modes to Conserve Power  
–
–
–
Active mode QVGA: 17 mW  
Typical Shutdown: 0.7 μW  
Typical Standby Mode: 27 μW Typical  
The parallel (CMOS) output bus offers a bus-swap  
feature. The SWAP control pin controls the output  
pin order of the output pixel data to be either R[7:0].  
G[7:0], B[7:0], VS, HS, DE or B[0:7], G[0:7], R[0:7],  
VS, HS, DE. This gives a PCB designer the flexibility  
to better match the bus to the LCD driver pinout or to  
put the receiver device on the top side or the bottom  
side of the PCB. The F/S control input selects  
between a slow CMOS bus output rise time for best  
EMI and power consumption and a fast CMOS  
output for increased speed or higher-load designs.  
•
•
•
•
•
Bus-Swap Function for PCB-Layout Flexibility  
ESD Rating > 4 kV (HBM)  
Pixel Clock Range of 4 MHz–15 MHz  
Failsafe on all CMOS Inputs  
Packaged in 5-mm × 5-mm MicroStar Junior  
μBGA® With 0,5-mm Ball Pitch  
•
Very Low EMI Meets SAE J1752/3 Kh-Spec  
APPLICATIONS  
•
Small Low-Emission Interface Between  
Graphics Controller and LCD Display  
•
•
Mobile Phones and Smart Phones  
Portable Multimedia Players  
LCD  
Driver  
Flatlinkä3G  
DESCRIPTION  
The  
SN65LVDS306  
receiver  
deserializes  
LVDS306  
CLK DATA  
LVDS305  
FlatLink™3G-compliant serial input data to 27  
parallel data outputs. The SN65LVDS306 receiver  
contains one shift register to load 30 bits from one  
serial input and latches the 24 pixel bits and 3 control  
bits out to the parallel CMOS outputs after checking  
the parity bit. If the parity check confirms correct  
parity, the channel parity error (CPE) output remains  
low. If a parity error is detected, the CPE output  
generates a high pulse while the data output bus  
disregards the newly-received pixel. Instead, the last  
data word is held on the output bus for another clock  
cycle.  
Application  
Processor  
with  
1
4
7
3
6
9
#
2
5
8
0
RGB  
Video  
Interface  
*
M0056-02  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
FlatLink is a trademark of Texas Instruments.  
μBGA is a registered trademark of Tessera, Inc.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2006–2007, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...31

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SN65LVDS306ZQER 替代型号

型号 品牌 替代类型 描述 数据表
SN65LVDS305ZQE TI

类似代替

 PROGRAMMABLE 27-BIT DISPLAY SERIAL INTERFACE TRANSMITTER
SN65LVDS305ZQER TI

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