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SN65LVDS302ZXH PDF预览

SN65LVDS302ZXH

更新时间: 2024-11-07 02:50:55
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
49页 2695K
描述
SN65LVDS302 Programmable 27-Bit Serial-to-Parallel Receiver

SN65LVDS302ZXH 数据手册

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SN65LVDS302  
SLLS733E – JUNE 2006 – REVISED OCTOBER 2020  
SN65LVDS302 Programmable 27-Bit Serial-to-Parallel Receiver  
1 Features  
3 Description  
Serial interface technology  
Compatible with FlatLink3G such as  
SN65LVDS301  
The  
SN65LVDS302  
receiver  
de-serializes  
FlatLink™3G compliant serial input data to 27 parallel  
data outputs. The SN65LVDS302 receiver contains  
one shift register to load 30 bits from 1, 2 or 3 serial  
inputs and latches the 24 pixel bits and 3 control bits  
out to the parallel CMOS outputs after checking the  
parity bit. If the parity check confirms correct parity,  
the Channel Parity Error (CPE) output remains low. If  
a parity error is detected, the CPE output generates a  
high pulse while the data output bus disregards the  
newly-received pixel. Instead, the last data word is  
held on the output bus for another clock cycle.  
Supports video interfaces up to 24-bit RGB data  
and 3 control bits received over 1, 2 or 3 SubLVDS  
differential lines  
SubLVDS differential voltage levels  
Up to 1.755-Gbps Data Throughput  
Three operating modes to conserve power  
– Active mode QVGA: 17 mW  
– Typical shutdown: 0.7 μW  
– Typical standby mode: 27 μW Typical  
Bus-swap function for PCB-layout flexibility  
ESD rating > 4 kV (HBM)  
Pixel clock range of 4 MHz to 65 MHz  
Failsafe on all CMOS inputs  
Device Information (1)  
PART NUMBER  
PACKAGE  
BODY SIZE (NOM)  
SN65LVDS302  
nFBGA (80)  
5.00 mm × 5.00 mm  
(1) For all available packages, see the orderable addendum at  
the end of the data sheet.  
Packaged in 5-mm × 5-mm nFBGA with 0.5-mm  
ball pitch  
Very low EMI meets SAE J1752/3 'Kh'-spec  
2 Applications  
Wearables (non-medical)  
Tablets  
Mobile phones  
Portable electronics  
Gaming  
Retail automation & payment  
Building automation  
LCD  
VDS314  
L
or  
VDS302  
L
Application  
Processor  
with CMOS  
Video Interface  
LVDS301  
or  
LVDS311  
Implementation Example  
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,  
intellectual property matters and other important disclaimers. PRODUCTION DATA.  
 
 
 

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