5秒后页面跳转
捷配首页

Datasheet > 驱动程序和接口 > 线路驱动器或接收器> SN65LVDS303
SN65LVDS303 PDF预览

SN65LVDS303

更新时间： 2024-11-27 05:25:03
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
30页 884K
描述
PROGRAMMABLE 27-BIT DISPLAY SERIAL-INTERFACE TRANSMITTER

阅读下载

中文翻译

获取价格

SN65LVDS303 数据手册

 浏览型号SN65LVDS303的Datasheet PDF文件第2页浏览型号SN65LVDS303的Datasheet PDF文件第3页浏览型号SN65LVDS303的Datasheet PDF文件第4页浏览型号SN65LVDS303的Datasheet PDF文件第5页浏览型号SN65LVDS303的Datasheet PDF文件第6页浏览型号SN65LVDS303的Datasheet PDF文件第7页 
SN65LVDS303  
www.ti.com  
SLLS743A–JULY 2006–REVISED JANUARY 2007  
PROGRAMMABLE 27-BIT DISPLAY SERIAL-INTERFACE TRANSMITTER  
FPC  
cabling  
typically  
interconnects  
the  
FEATURES  
SN65LVDS303 with the display. Compared to  
parallel signaling, the SN65LVDS303 outputs  
significantly reduce the EMI of the interconnect by  
over 20 dB.  
•
FlatLink™3G Serial-Interface Technology  
•
Compatible With FlatLink3G Receivers Such  
as SN65LVDS304  
•
•
Input Supports 24-bit RGB Video Mode  
Interface  
The SN65LVDS303 supports three power modes  
(shutdown, standby and active) to conserve power.  
When transmitting, the PLL locks to the incoming  
pixel clock, PCLK, and generates an internal  
high-speed clock at the line rate of the data lines.  
The parallel data are latched on the rising or falling  
edge of PCLK, as selected by the external control  
signal CPOL. The serialized data is presented on the  
serial outputs D0 and D1, together with a recreated  
PCLK that is generated from the internal high-speed  
clock and output on CLK. If PCLK stops, the device  
enters a standby mode to conserve power.  
24-Bit RGB Data, 3 Control Bits, 1 Parity Bit  
and 2 Reserved Bits Transmitted over 1 or 2  
Differential Lines  
•
•
•
SubLVDS Differential Voltage Levels  
Effective Data Throughput up to 810 Mbps  
Three Operating Modes to Conserve Power  
–
–
–
–
Active-Mode QVGA 17.4 mW (typ)  
Active-Mode VGA 28.8 mW (typ)  
Shutdown Mode ≈ 0.5 µA (typ)  
Standby Mode ≈ 0.5 µA (typ)  
The parallel (CMOS) input bus offers a bus-swap  
feature. The SWAP terminal configures the input  
order of the pixel data to be either R[7:0], G[7:0],  
B[7:0], VS, HS, DE or B[0:7]. G[0:7], R[0:7], VS, HS,  
DE. This gives a PCB designer the flexibility to better  
match the bus to the host controller pinout or to put  
the transmitter device on the top side or the bottom  
side of the PCB.  
•
Bus Swap for Increased PCB Layout  
Flexibility  
•
•
•
1.8-V Supply Voltage  
ESD Rating > 2 kV (HBM)  
Typical Application: Host-Controller to  
Display-Module Interface  
•
•
•
Pixel Clock Range of 4 MHz–30 MHz  
Failsafe on All CMOS Inputs  
Packaging: 80-Terminal, 5-mm × 5-mm µBGA®  
LCD  
Driver  
Flatlinkä3G  
DESCRIPTION  
The SN65LVDS303 serializer device converts 27  
parallel data inputs to one or two sub-low-voltage  
differential signaling (SubLVDS) serial outputs. It  
loads a shift register with 24 pixel bits and 3 control  
bits from the parallel CMOS input interface. In  
addition to the 27 data bits, the device adds a parity  
bit and two reserved bits into a 30-bit data word.  
Each word is latched into the device by the pixel  
clock (PCLK). The parity bit (odd parity) allows a  
receiver to detect single bit errors. The serial shift  
register is uploaded at 30 or 15 times the pixel-clock  
data rate, depending on the number of serial links  
used. A copy of the pixel clock is output on a  
separate differential output.  
LVDS304  
CLK DATA  
LVDS303  
Application  
Processor  
with  
1
4
7
3
6
9
#
2
5
8
0
RGB  
Video  
Interface  
*
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
FlatLink is a trademark of Texas Instruments.  
µBGA is a registered trademark of Tessera, Inc..  
All other trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2006–2007, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...30

中文翻译

下载PDF

SN65LVDS303 替代型号

型号 品牌 替代类型 描述 数据表
SN65LVDS306 TI

功能相似

 PROGRAMMABLE 27-BIT SERIAL-TO-PARALLEL RECEIVER
SN65LVDS301 TI

功能相似

 PROGRAMMABLE 27-BIT DISPLAY SERIAL INTERFACE TRANSMITTER

与SN65LVDS303相关器件

型号 品牌 获取价格 描述 数据表
SN65LVDS303ZQE TI

获取价格

 		LINE DRIVER, PBGA80, 5 X 5 MM, PLASTIC, MICRO, BGA-80
SN65LVDS303ZQER TI

获取价格

 		PROGRAMMABLE 27-BIT DISPLAY SERIAL-INTERFACE TRANSMITTER
SN65LVDS304 TI

获取价格

 		PROGRAMMABLE 27-BIT PARALLEL-TO-SERIAL RECEIVER
SN65LVDS304ZQER TI

获取价格

 		PROGRAMMABLE 27-BIT PARALLEL-TO-SERIAL RECEIVER
SN65LVDS305 TI

获取价格

 		PROGRAMMABLE 27-BIT DISPLAY SERIAL INTERFACE TRANSMITTER
SN65LVDS305ZQE TI

获取价格

 		PROGRAMMABLE 27-BIT DISPLAY SERIAL INTERFACE TRANSMITTER
SN65LVDS305ZQER TI

获取价格

 		PROGRAMMABLE 27-BIT DISPLAY SERIAL INTERFACE TRANSMITTER
SN65LVDS306 TI

获取价格

 		PROGRAMMABLE 27-BIT SERIAL-TO-PARALLEL RECEIVER
SN65LVDS306ZQER TI

获取价格

 		PROGRAMMABLE 27-BIT SERIAL-TO-PARALLEL RECEIVER
SN65LVDS307 TI

获取价格

 		PROGRAMMABLE 27-BIT PARALLEL-TO-SERIAL TRANSMITTER

与SN65LVDS303相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证