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SN65LVDS302ZQE PDF预览

SN65LVDS302ZQE

更新时间： 2024-11-25 03:56:51
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
41页 1437K
描述
PROGRAMMABLE 27-BIT SERIAL-TO-PARALLEL RECEIVER

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SN65LVDS302ZQE 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：BGA
包装说明：VFBGA, BGA80,9X9,20针数：80
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：1.97
差分输出：NO驱动器位数：3
高电平输入电流最大值：0.00002 A输入特性：DIFFERENTIAL
接口集成电路类型：LINE RECEIVER接口标准：GENERAL PURPOSE
JESD-30 代码：S-PBGA-B80JESD-609代码：e1
长度：5 mm湿度敏感等级：3
功能数量：1端子数量：80
最高工作温度：85 °C最低工作温度：-40 °C
最大输出低电流：0.002 A输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：VFBGA
封装等效代码：BGA80,9X9,20封装形状：SQUARE
封装形式：GRID ARRAY, VERY THIN PROFILE, FINE PITCH峰值回流温度（摄氏度）：260
电源：1.8 V认证状态：Not Qualified
最大接收延迟：接收器位数：3
座面最大高度：1 mm子类别：Line Driver or Receivers
最大压摆率：68 mA最大供电电压：1.95 V
最小供电电压：1.65 V标称供电电压：1.8 V
电源电压1-最大：1.95 V电源电压1-分钟：1.65 V
电源电压1-Nom：1.8 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Silver/Copper (Sn/Ag/Cu)端子形式：BALL
端子节距：0.5 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：5 mm
Base Number Matches：1

SN65LVDS302ZQE 数据手册

 浏览型号SN65LVDS302ZQE的Datasheet PDF文件第2页浏览型号SN65LVDS302ZQE的Datasheet PDF文件第3页浏览型号SN65LVDS302ZQE的Datasheet PDF文件第4页浏览型号SN65LVDS302ZQE的Datasheet PDF文件第5页浏览型号SN65LVDS302ZQE的Datasheet PDF文件第6页浏览型号SN65LVDS302ZQE的Datasheet PDF文件第7页 
SN65LVDS302  
www.ti.com  
SLLS733A–JUNE 2006–REVISED AUGUST 2006  
PROGRAMMABLE 27-BIT SERIAL-TO-PARALLEL RECEIVER  
The serial data and clock are received via Sub  
Low-Voltage Differential Signalling (SubLVDS) lines.  
The SN65LVDS302 supports three operating power  
modes (Shutdown, Standby, and Active) to conserve  
power.  
FEATURES  
•
Serial Interface Technology  
•
Compatible with FlatLink™3G such as  
SN65LVDS301  
•
Supports Video Interfaces up to 24-bit RGB  
Data and 3 Control Bits Received over 1, 2 or  
3 SubLVDS Differential Lines  
When receiving, the PLL locks to the incoming clock  
CLK and generates an internal high-speed clock at  
the line rate of the data lines. The data is serially  
loaded into  
a shift register using the internal  
•
•
•
SubLVDS Differential Voltage Levels  
Up to 1.755 Gbps Data Throughput  
Three Operating Modes to Conserve Power  
– Active mode QVGA - 17 mW  
high-speed clock. The deserialized data is presented  
on the parallel output bus with a recreation of the  
Pixel clock PCLK generated from the internal  
high-speed clock. If no input CLK signal is present,  
the output bus is held static with the PCLK and DE  
held low, while all other parallel outputs are pulled  
high.  
– Typical Shutdown - 0.7 µW  
– Typical Standby Mode - 27 µW Typical  
Bus-Swap Function for PCB-Layout Flexibility  
ESD Rating > 4 kV (HBM)  
•
•
•
•
•
The parallel (CMOS) output bus offers a bus-swap  
feature. The SWAP control pin controls the output  
pin order of the output pixel data to be either R[7:0].  
G[7:0], B[7:0], VS, HS, DE or B[0:7], G[0:7], R[0:7],  
VS, HS, DE. This gives a PCB designer the flexibility  
to better match the bus to the LCD driver pinout or to  
put the receiver device on the top side or the bottom  
side of the PCB. The F/S control input selects  
between a slow CMOS bus output rise time for best  
EMI and power consumption and a fast CMOS  
output for increased speed or higher load designs.  
Pixel Clock Range of 4 MHz–65 MHz  
Failsafe on all CMOS Inputs  
Packaged in 5 mm x 5 mm MicroStar Junior  
µBGA® with 0,5 mm Ball Pitch  
•
Very low EMI meets SAE J1752/3 'Kh'-spec  
APPLICATIONS  
•
Small Low-Emission Interface between  
Graphics Controller and LCD Display  
•
•
Mobile Phones & Smart Phones  
Portable Multimedia Players  
LCD  
Driver  
Flatlinkä3G  
DESCRIPTION  
The  
SN65LVDS302  
receiver  
de-serializes  
LVDS302  
CLK DATA  
LVDS301  
FlatLink™3G compliant serial input data to 27  
parallel data outputs. The SN65LVDS302 receiver  
contains one shift register to load 30 bits from 1, 2 or  
3 serial inputs and latches the 24 pixel bits and 3  
control bits out to the parallel CMOS outputs after  
checking the parity bit. If the parity check confirms  
correct parity, the Channel Parity Error (CPE) output  
remains low. If a parity error is detected, the CPE  
output generates a high pulse while the data output  
bus disregards the newly-received pixel. Instead, the  
last data word is held on the output bus for another  
clock cycle.  
Application  
Processor  
with  
1
4
7
3
6
9
#
2
5
8
0
RGB  
Video  
Interface  
*
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
FlatLink is a trademark of Texas Instruments.  
µBGA is a registered trademark of Tessera, Inc.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2006, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...41

中文翻译

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SN65LVDS302ZQE 替代型号

型号 品牌 替代类型 描述 数据表
SN65LVDS304ZQER TI

完全替代

 PROGRAMMABLE 27-BIT PARALLEL-TO-SERIAL RECEIVER
SN65LVDS302ZQER TI

类似代替

 PROGRAMMABLE 27-BIT SERIAL-TO-PARALLEL RECEIVER

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SN65LVDS304 TI

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