Datasheet > SN65LVDS301_V01

SN65LVDS301_V01

更新时间： 2024-11-26 02:50:55

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德州仪器 - TI		/
页数	文件大小	规格书
43页	2387K
描述
SN65LVDS301 Programmable 27-Bit Parallel-to-Serial Transmitter

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SN65LVDS301_V01 数据手册

SN65LVDS301

www.ti.com

SLLS681E – FEBRUARY 2006 – REVISED OCTOBER 2020

SN65LVDS301 Programmable 27-Bit Parallel-to-Serial Transmitter

1 Features

3 Description

•

FlatLink^™3G serial interface technology

Compatible with FlatLink3G receivers such as

SN65LVDS302

The SN65LVDS301 serializer device converts 27

parallel data inputs to 1, 2, or 3 Sub Low-Voltage

Differential Signaling (SubLVDS) serial outputs. It

loads a shift register with 24 pixel bits and 3 control

bits from the parallel CMOS input interface. In addition

to the 27 data bits, the device adds a parity bit and

two reserved bits into a 30-bit data word. Each word is

latched into the device by the pixel clock (PCLK). The

parity bit (odd parity) allows a receiver to detect single

bit errors. The serial shift register is uploaded at 30,

15, or 10 times the pixel-clock data rate depending on

the number of serial links used. A copy of the pixel

clock is output on a separate differential output.

•

Input supports 24-bit RGB video mode interface

24-Bit RGB data, 3 control bits, 1 parity bit and 2

reserved bits transmitted over 1, 2 or 3 differential

lines

SubLVDS differential voltage levels

Effective data throughput up to 1755 Mbps

Three operating modes to conserve power

– Active-mode QVGA 17.4 mW (typ)

– Active-mode VGA 28.8 mW (typ)

– Shutdown mode 0.5 μA (typ)

– Standby mode 0.5 μA (typ)

Bus swap for increased PCB layout flexibility

1.8-V supply voltage

ESD rating > 2 kV (HBM)

Pixel clock range of 4 MHz–65 MHz

Failsafe on all CMOS inputs

•

FPC

cabling

typically

interconnects

the

SN65LVDS301 with the display. Compared to parallel

signaling, the LVDS301 outputs significantly reduce

the EMI of the interconnect by over 20 dB. The

electromagnetic emission of the device itself is very

low and meets the meets SAE J1752/3 'M'-spec. (see

Figure 6-22)

•

Packaging: 80 pin 5mm × 5mm nFBGA^®

Very low EMI meets SAE J1752/3 'M'-spec

The SN65LVDS301 is characterized for operation

over ambient air temperatures of –40°C to 85°C. All

CMOS inputs offer failsafe features to protect them

from damage during power-up and to avoid current

flow into the device inputs during power-up. An input

voltage of up to 2.165 V can be applied to all CMOS

inputs while V_DDis between 0V and 1.65V.

2 Applications

•

Wearables (non-medical)

Tablets

Mobile phones

Portable electronics

Gaming

Retail automation & payment

Building automation

Device Information ⁽¹⁾

PART NUMBER

PACKAGE

BODY SIZE (NOM)

SN65LVDS301

nFBGA (80)

5.00 mm × 5.00 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

LCD

VDS314

VDS302

Application

Processor

with CMOS

Video Interface

LVDS301

LVDS311

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

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Product Folder Links: SN65LVDS301

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与SN65LVDS301_V01相关器件

型号	品牌	获取价格	描述	数据表
SN65LVDS301ZQE	TI	获取价格	PROGRAMMABLE 27-BIT DISPLAY SERIAL INTERFACE TRANSMITTER
SN65LVDS301ZQER	TI	获取价格	PROGRAMMABLE 27-BIT DISPLAY SERIAL INTERFACE TRANSMITTER
SN65LVDS301ZXH	TI	获取价格	SN65LVDS301 Programmable 27-Bit Parallel-to-Serial Transmitter
SN65LVDS301ZXHR	TI	获取价格	SN65LVDS301 Programmable 27-Bit Parallel-to-Serial Transmitter
SN65LVDS302	TI	获取价格	PROGRAMMABLE 27-BIT SERIAL-TO-PARALLEL RECEIVER
SN65LVDS302_07	TI	获取价格	PROGRAMMABLE 27-BIT SERIAL-TO-PARALLEL RECEIVER
SN65LVDS302_V01	TI	获取价格	SN65LVDS302 Programmable 27-Bit Serial-to-Parallel Receiver
SN65LVDS302ZQE	TI	获取价格	PROGRAMMABLE 27-BIT SERIAL-TO-PARALLEL RECEIVER
SN65LVDS302ZQER	TI	获取价格	PROGRAMMABLE 27-BIT SERIAL-TO-PARALLEL RECEIVER
SN65LVDS302ZXH	TI	获取价格	SN65LVDS302 Programmable 27-Bit Serial-to-Parallel Receiver

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