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SN65LVDS301ZQE PDF预览

SN65LVDS301ZQE

更新时间： 2024-11-06 03:56:51
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
34页 1819K
描述
PROGRAMMABLE 27-BIT DISPLAY SERIAL INTERFACE TRANSMITTER

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SN65LVDS301ZQE 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：BGA
包装说明：VFBGA, BGA80,9X9,20针数：80
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：1.36
差分输出：YES驱动器位数：1
高电平输入电流最大值：0.00002 A输入特性：DIFFERENTIAL
接口集成电路类型：LINE DRIVER接口标准：GENERAL PURPOSE
JESD-30 代码：S-PBGA-B80JESD-609代码：e1
长度：5 mm湿度敏感等级：3
功能数量：1端子数量：80
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：DIFFERENTIAL输出极性：COMPLEMENTARY
封装主体材料：PLASTIC/EPOXY封装代码：VFBGA
封装等效代码：BGA80,9X9,20封装形状：SQUARE
封装形式：GRID ARRAY, VERY THIN PROFILE, FINE PITCH峰值回流温度（摄氏度）：260
电源：1.8 V认证状态：Not Qualified
最大接收延迟：座面最大高度：1 mm
子类别：Line Driver or Receivers最大压摆率：36.8 mA
最大供电电压：1.95 V最小供电电压：1.65 V
标称供电电压：1.8 V电源电压1-最大：1.95 V
电源电压1-分钟：1.65 V电源电压1-Nom：1.8 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：BALL端子节距：0.5 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：5 mmBase Number Matches：1

SN65LVDS301ZQE 数据手册

 浏览型号SN65LVDS301ZQE的Datasheet PDF文件第2页浏览型号SN65LVDS301ZQE的Datasheet PDF文件第3页浏览型号SN65LVDS301ZQE的Datasheet PDF文件第4页浏览型号SN65LVDS301ZQE的Datasheet PDF文件第5页浏览型号SN65LVDS301ZQE的Datasheet PDF文件第6页浏览型号SN65LVDS301ZQE的Datasheet PDF文件第7页 
SN65LVDS301  
www.ti.com  
SLLS681C–FEBRUARY 2006–REVISED AUGUST 2006  
PROGRAMMABLE 27-BIT DISPLAY SERIAL INTERFACE TRANSMITTER  
FPC  
cabling  
typically  
interconnects  
the  
FEATURES  
SN65LVDS301 with the display. Compared to  
parallel signaling, the LVDS301 outputs significantly  
reduce the EMI of the interconnect by over 20 dB.  
The electromagnetic emission of the device itself is  
very low and meets the meets SAE J1752/3  
'M'-spec. (see Figure 37)  
•
FlatLink™3G serial interface technology  
•
Compatible with FlatLink3G receivers such as  
SN65LVDS302  
•
•
Input supports 24-bit RGB video mode  
interface  
24-Bit RGB Data, 3 Control Bits, 1 Parity Bit  
and 2 Reserved Bits Transmitted over 1, 2 or 3  
Differential Lines  
The SN65LVDS301 supports three power modes  
(Shutdown, Standby and Active) to conserve power.  
When transmitting, the PLL locks to the incoming  
pixel clock PCLK and generates an internal  
high-speed clock at the line rate of the data lines.  
The parallel data are latched on the rising or falling  
edge of PCLK as selected by the external control  
signal CPOL. The serialized data is presented on the  
serial outputs D0, D1, D2 with a recreated PCLK  
generated from the internal high-speed clock, output  
on the CLK output. If PCLK stops, the device enters  
a standby mode to conserve power  
•
•
•
SubLVDS Differential Voltage Levels  
Effective Data Throughput up to 1755 Mbps  
Three Operating Modes to Conserve Power  
–
–
–
–
Active-Mode QVGA 17.4 mW (typ)  
Active-Mode VGA 28.8 mW (typ)  
Shutdown Mode ≈ 0.5 µA (typ)  
Standby Mode ≈ 0.5 µA (typ)  
The parallel (CMOS) input bus offers a bus-swap  
feature. The SWAP pin configures the input order of  
the pixel data to be either R[7:0]. G[7:0], B[7:0], VS,  
HS, DE or B[0:7]. G[0:7], R[0:7], VS, HS, DE. This  
gives a PCB designer the flexibility to better match  
the bus to the host controller pinout or to put the  
transmitter device on the top side or the bottom side  
of the PCB.  
•
Bus Swap for Increased PCB Layout  
Flexibility  
•
•
•
1.8-V Supply Voltage  
ESD Rating > 2 kV (HBM)  
Typical Application: Host-Controller to  
Display-Module Interface  
•
•
•
•
Pixel Clock Range of 4 MHz–65 MHz  
Failsafe on all CMOS Inputs  
Packaging: 80 Pin 5mm × 5mm µBGA®  
Very low EMI meets SAE J1752/3 'M'-spec  
LCD  
Driver  
Flatlinkä3G  
DESCRIPTION  
The SN65LVDS301 serializer device converts 27  
parallel data inputs to 1, 2, or 3 Sub Low-Voltage  
Differential Signaling (SubLVDS) serial outputs. It  
loads a shift register with 24 pixel bits and 3 control  
bits from the parallel CMOS input interface. In  
addition to the 27 data bits, the device adds a parity  
bit and two reserved bits into a 30-bit data word.  
Each word is latched into the device by the pixel  
clock (PCLK). The parity bit (odd parity) allows a  
receiver to detect single bit errors. The serial shift  
register is uploaded at 30, 15, or 10 times the  
pixel-clock data rate depending on the number of  
serial links used. A copy of the pixel clock is output  
on a separate differential output.  
LVDS302  
CLK DATA  
LVDS301  
Application  
Processor  
with  
1
4
7
3
6
9
#
2
5
8
0
RGB  
Video  
Interface  
*
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
FlatLink is a trademark of Texas Instruments.  
µBGA is a registered trademark of Tessera, Inc..  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2006, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...34

中文翻译

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SN65LVDS301ZQE 替代型号

型号 品牌 替代类型 描述 数据表
SN65LVDS305ZQER TI

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