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SMJ55161 PDF预览

SMJ55161

更新时间： 2024-09-08 03:31:35
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
64页 1539K
描述
262144 BY 16-BIT MULTIPORT VIDEO RAM

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SMJ55161 数据手册

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SMJ55161  
262144 BY 16-BIT  
MULTIPORT VIDEO RAM  
SGMS056D – MAY 1995 – REVISED OCTOBER 1997  
HKC PACKAGE  
(TOP VIEW)  
Organization:  
– DRAM: 262 144 by 16 Bits  
– SAM: 256 by 16 Bits  
V
1
2
3
4
5
6
7
8
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
SC  
SE  
V
CC  
TRG  
Dual-Port Accessibility – Simultaneous and  
Asynchronous Access From the DRAM and  
SAM Ports  
V
SS  
SS  
SQ0  
DQ0  
SQ1  
DQ1  
SQ15  
DQ15  
SQ14  
DQ14  
Data-Transfer Function From the DRAM to  
the Serial-Data Register  
V
V
CC  
CC  
SQ2  
SQ13  
DQ13  
SQ12  
DQ12  
9
10  
11  
DQ2  
SQ3  
DQ3  
(4 × 4) × 4 Block-Write Feature for Fast  
Area-Fill Operations; as Many as Four  
Memory-Address Locations Written Per  
Cycle From the 16-Bit On-Chip Color  
Register  
54  
53  
52  
51  
50  
49  
12  
13  
V
V
SS  
SS  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
SQ4  
DQ4  
SQ5  
SQ11  
DQ11  
SQ10  
DQ5  
V
DQ10  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
Write-Per-Bit Feature for Selective Write to  
Each RAM I/O; Two Write-Per-Bit Modes to  
Simplify System Design  
V
CC  
CC  
SQ6  
DQ6  
SQ7  
DQ7  
SQ9  
DQ9  
SQ8  
DQ8  
Byte-Write Control (CASL, CASU) Provides  
Flexibility  
V
V
SS  
SS  
CASL  
DSF  
NC / GND  
CASU  
QSF  
A0  
WE  
RAS  
A8  
Extended Data Output for Faster System  
Cycle Time  
A7  
Enhanced Page-Mode Operation for Faster  
Access  
A6  
29  
30  
31  
A1  
A5  
A4  
A2  
A3  
CAS-Before-RAS (CBR) and  
Hidden-Refresh Modes  
V
32  
V
CC  
SS  
Long Refresh Period  
Programmable Split-Register Stop Point  
Every 8 ms (Maximum)  
3-State Serial Outputs Allow Easy  
Multiplexing of Video-Data Streams  
Up to 45-MHz Uninterrupted Serial-Data  
Streams  
All Inputs/Outputs and Clocks TTL  
Compatible  
256 Selectable Serial-Register Starting  
Locations  
Compatible With JEDEC Standards  
SE-Controlled Register-Status QSF  
Designed to Work With the Texas  
Instruments Graphics Family  
Split-Register-Transfer Read for Simplified  
Real-Time Register Load  
Performance Ranges:  
OPERATING CURRENT  
OPERATING CURRENT  
ACCESS TIME ACCESS TIME  
DRAM  
DRAM  
SERIAL  
ROW ENABLE  
SERIAL DATA CYCLE TIME PAGE MODE CYCLE TIME  
SERIAL PORT STAND- SERIAL PORT AC-  
t
t
t
t
t
I
I
CC1A  
BY  
TIVE  
a(R)  
a(SQ)  
c(W)  
c(P)  
c(SC)  
CC1  
(MAX)  
(MAX)  
(MIN)  
(MIN)  
(MIN)  
(MAX)  
(MAX)  
SMJ55161-75  
SMJ55161-80  
75 ns  
80 ns  
23 ns  
25 ns  
140 ns  
150 ns  
48 ns  
50 ns  
24 ns  
30 ns  
165 mA  
160 mA  
210 mA  
195 mA  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1997, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
1234567...64

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SMJ55161-70GBM TI

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 		256KX16 VIDEO DRAM, 70ns, CPGA68, CERAMIC, PGA-68
SMJ55161-70HKCM TI

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 		256KX16 VIDEO DRAM, 70ns, CDFP64, CERAMIC, DFP-64
SMJ55161AGB-70 MICROSS

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 		Memory Circuit, 256KX16, PPGA68
SMJ55161AGB-80 MICROSS

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 		Memory Circuit, 256KX16, PPGA68
SMJ55161AHKC-70 MICROSS

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 		Memory Circuit, 256KX16, CQFP64
SMJ55161AHKC-75 MICROSS

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 		Memory Circuit, 256KX16, CQFP64
SMJ55165-80HKCM TI

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 		256KX16 VIDEO DRAM, 80ns, CDFP64, 0.50 MM FINE PITCH, CERAMIC, FP-64
SMJ55166 TI

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 		262144 BY 16-BIT MULTIPORT VIDEO RAM
SMJ55166-70GB TI

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 		256KX16 VIDEO DRAM, 70ns, CPGA68
SMJ55166-70HKC TI

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 		256KX16 VIDEO DRAM, 70ns, CDFP64

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