SMJ55166
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SGMS057C – APRIL 1995 – REVISED JUNE 1997
Organization:
– DRAM: 262144 Words × 16 Bits
– SAM: 256 Words × 16 Bits
Enhanced Page-Mode Operation for Faster
Access
CAS-Before-RAS (CBR) and
Hidden-Refresh Modes
Dual-Port Accessibility – Simultaneous and
Asynchronous Access From the DRAM and
SAM Ports
Long Refresh Period
Every 8 ms (Max)
Data-Transfer Function From the DRAM to
the Serial-Data Register
Up to 45-MHz Uninterrupted Serial-Data
Streams
(4 × 4) × 4 Block-Write Feature for Fast
Area-Fill Operations; as Many as Four
Memory-Address Locations Written Per
Cycle From the 16-Bit On-Chip Color
Register
256 Selectable Serial-Register Starting
Locations
SE-Controlled Register-Status QSF
Split-Register-Transfer Read for Simplified
Real-Time Register Load
Write-Per-Bit Feature for Selective Write to
Each RAM I/O; Two Write-Per-Bit Modes to
Simplify System Design
Programmable Split-Register Stop Point
3-State Serial Outputs Allow Easy
Multiplexing of Video-Data Streams
Byte-Write Control (WEL, WEU) Provides
Flexibility
All Inputs/Outputs and Clocks
TTL-Compatible
Extended Data Output (EDO) for Faster
System Cycle Time
Compatible With JEDEC Standards
Designed to Work With the
Texas Instruments Graphics Family
Performance Ranges:
ACCESS TIME ACCESS TIME
DRAM
DRAM
SERIAL
OPERATING CURRENT
OPERATING CURRENT
ROW ENABLE
SERIAL DATA CYCLE TIME PAGE MODE CYCLE TIME
SERIALPORT STAND- SERIALPORT
AC-
t
t
t
t
t
I
I
CC1A
a(R)
a(SQ)
c(W)
c(P)
c(SC)
BY
CC1
TIVE
(MAX)
(MAX)
(MIN)
(MIN)
(MIN)
(MAX)
(MAX)
SMJ55166-75
SMJ55166-80
75 ns
80 ns
23 ns
25 ns
140 ns
150 ns
48 ns
50 ns
24 ns
30 ns
165 mA
160 mA
210 mA
195 mA
description
The SMJ55166 multiport video RAM is a high-speed, dual-ported memory device. It consists of a dynamic
random-access memory (DRAM) module organized as 262 144 words of 16 bits each that are interfaced to a
serial-data register (serial-access memory [SAM]) organized as 256 words of 16 bits each. The SMJ55166
supports three basic types of operation: random access to and from the DRAM, serial access from the serial
register, and transfer of data from any row in the DRAM to the serial register. Except during transfer operations,
the SMJ55166 can be accessed simultaneously and asynchronously from the DRAM and SAM ports.
The SMJ55166 is equipped with several features designed to provide higher system-level bandwidth and to
simplify design integration on both the DRAM and SAM ports. On the DRAM port, greater pixel draw rates are
achieved by the (4 × 4) × 4 block-write feature of the device. The block-write mode allows 16 bits of data (present
in an on-chip color-data register) to be written to any combination of four adjacent column-address locations.
As many as 64 bits of data can be written to memory during each CAS cycle time. Also on the DRAM port, a
write mask or a write-per-bit feature allows masking of any combination of the 16 inputs/outputs on any write
cycle. The persistent write-per-bit feature uses a mask register that, once loaded, can be used on subsequent
write cycles without reloading. The SMJ55166 also offers byte control, which can be applied in write cycles,
block-write cycles, load-write-mask-register cycles, and load-color-register cycles. The SMJ55166 also offers
extended-data-output (EDO) mode, which is effective in both the page-mode and standard DRAM cycles.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
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