Si4330-B1
Si4330 ISM RECEIVER
Features
Frequency Range = 240–960 MHz
Sensitivity = –121 dBm
Low Power Consumption
18.5 mA receive
Data Rate = 0.123 to 256 kbps
FSK, GFSK, and OOK modulation
Power Supply = 1.8 to 3.6 V
Ultra low power shutdown mode
Digital RSSI
Programmable GPIOs
Embedded antenna diversity
algorithm
Configurable packet handler
Preamble detector
RX 64 byte FIFO
Low battery detector
Temperature sensor and 8-bit ADC
–40 to +85 °C temperature range
Integrated voltage regulators
Frequency hopping capability
On-chip crystal tuning
20-Pin QFN package
Low BOM
Wake-up timer
Ordering Information:
Auto-frequency calibration (AFC)
Clear channel assessment
Programmable RX BW 2.6–620 kHz
Programmable packet handler
See page 63.
Pin Assignments
Si4330
Power-on-reset (POR)
Applications
Remote control
Home security & alarm
Telemetry
Personal data logging
Toy control
Tire pressure monitoring
Wireless PC peripherals
Remote meter reading
Remote keyless entry
Home automation
Industrial control
Sensor networks
Health monitors
20 19 18 17
VDD_RF
NC
1
16
2
15 SCLK
14 SDI
13 SDO
12 VDD_DIG
11 NC
RXp
RXn
NC
3
4
5
GND
PAD
Tag readers
6
7
8
9
10
Description
Silicon Laboratories’ Si4330 is a highly integrated, single chip wireless ISM
receiver. The high-performance EZRadioPRO® family includes a complete line of
transmitters, receivers, and transceivers allowing the RF system designer to
choose the optimal wireless part for their application.
Patents pending
The Si4330 offers advanced radio features including continuous frequency
coverage from 240–960 MHz. The Si4330’s high level of integration offers
reduced BOM cost while simplifying the overall system design. The extremely low
receive sensitivity (–121 dBm) ensures extended range and improved link
performance. Built-in antenna diversity and support for frequency hopping can be
used to further extend range and enhance performance.
Additional system features such as an automatic wake-up timer, low battery
detector, 64 byte RX FIFO, automatic packet handling, and preamble detection
reduce overall current consumption and allow the use of a lower-cost system
MCU. An integrated temperature sensor, general purpose ADC, power-on-reset
(POR), and GPIOs further reduce overall system cost and size.
The Si4330’s digital receive architecture features a high-performance ADC and
DSP based modem which performs demodulation, filtering, and packet handling
for increased flexibility and performance.
An easy-to-use calculator is provided to quickly configure the radio settings,
simplifying customer's system design and reducing time to market.
Rev 1.0 12/09
Copyright © 2009 by Silicon Laboratories
Si4330