MUN5311DW1T1G,
SMUN5311DW1T1G,
NSVMUN5311DW1T1GꢀSeries
Dual Bias Resistor
Transistors
http://onsemi.com
NPN and PNP Silicon Surface Mount
Transistors with Monolithic Bias
Resistor Network
SOT−363
CASE 419B
STYLE 1
The Bias Resistor Transistor (BRT) contains a single transistor with
a monolithic bias network consisting of two resistors; a series base
resistor and a base−emitter resistor. These digital transistors are
designed to replace a single device and its external resistor bias
network. The BRT eliminates these individual components by
(3)
(2)
(1)
R
1
R
2
integrating them into
a
single device. In the
Q
1
MUN5311DW1T1G series, two complementary BRT devices are
housed in the SOT−363 package which is ideal for low power surface
mount applications where board space is at a premium.
Q
2
R
2
R
1
(4)
(5)
(6)
Features
• Simplifies Circuit Design
• Reduces Board Space
MARKING DIAGRAM
6
• Reduces Component Count
• Available in 8 mm, 7 inch/3000 Unit Tape and Reel
xx M G
G
• S and NSV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q101
Qualified and PPAP Capable
1
xx
M
G
= Device Code
= Date Code*
= Pb−Free Package
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant*
(Note: Microdot may be in either location)
MAXIMUM RATINGS (T = 25°C unless otherwise noted, common for
A
*Date Code orientation and/or position may
vary depending upon manufacturing location.
Q and Q , − minus sign for Q (PNP) omitted)
1
2
1
Rating
Symbol
Value
50
Unit
Vdc
ORDERING AND DEVICE MARKING
INFORMATION
Collector-Base Voltage
Collector-Emitter Voltage
Collector Current
V
CBO
CEO
V
50
Vdc
See detailed ordering, shipping, and specific marking
information in the table on page 2 of this data sheet.
I
C
100
mAdc
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2012
1
Publication Order Number:
March, 2014 − Rev. 14
MUN5311DW1T1/D