Datasheet > NSVB123JPDXV6T1G

NSVB123JPDXV6T1G

更新时间： 2024-01-19 14:01:15

品牌	Logo	应用领域
安森美 - ONSEMI		晶体晶体管
页数	文件大小	规格书
15页	181K
描述
Dual Bias Resistor Transistors

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NSVB123JPDXV6T1G 数据手册

NSBC114EPDXV6T1G,

NSVBC114EPDXV6T1G Series

Dual Bias Resistor

Transistors

NPN and PNP Silicon Surface Mount

Transistors with Monolithic Bias

Resistor Network

http://onsemi.com

The BRT (Bias Resistor Transistor) contains a single transistor with

a monolithic bias network consisting of two resistors; a series base

resistor and a base−emitter resistor. These digital transistors are

designed to replace a single device and its external resistor bias

network. The BRT eliminates these individual components by

integrating them into a single device. In the NSBC114EPDXV6T1

series, two complementary BRT devices are housed in the SOT−563

package which is ideal for low power surface mount applications

where board space is at a premium.

SOT−563

CASE 463A

PLASTIC

(3)

(2)

(1)

Features

• Simplifies Circuit Design

• Reduces Board Space

• Reduces Component Count

• Available in 8 mm, 7 inch Tape and Reel

• AEC−Q101 Qualified and PPAP Capable

(4)

(5)

(6)

MARKING DIAGRAM

• NSV Prefix for Automotive and Other Applications Requiring

Unique Site and Control Change Requirements

• These are Pb−Free Devices*

xx MG

xx = Specific Device Code

(see table on page 2)

MAXIMUM RATINGS (T = 25°C unless otherwise noted, common for Q

= Date Code

= Pb−Free Package

and Q , − minus sign for Q (PNP) omitted)

Rating

Symbol

Value

Unit

Vdc

(Note: Microdot may be in either location)

Collector-Base Voltage

Collector-Emitter Voltage

Collector Current

CBO

CEO

ORDERING INFORMATION

Vdc

†

Device

Package

Shipping

100

mAdc

Stresses exceeding Maximum Ratings may damage the device. Maximum

Ratings are stress ratings only. Functional operation above the Recommended

Operating Conditions is not implied. Extended exposure to stresses above the

Recommended Operating Conditions may affect device reliability.

NSBC114EPDXV6T1G SOT−563

4 mm pitch

4000/Tape & Reel

NSBC114EPDXV6T5G SOT−563

2 mm pitch

8000/Tape & Reel

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specification

Brochure, BRD8011/D.

DEVICE MARKING INFORMATION

See specific marking information in the device marking table

on page 2 of this data sheet.

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

Publication Order Number:

January, 2012 − Rev. 7

NSBC114EPDXV6/D

12 3 4 5 6 7...15

中文翻译

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