Datasheet > MPC9658ACR2

MPC9658ACR2

更新时间： 2024-11-12 14:53:55

品牌	Logo	应用领域
艾迪悌 - IDT		驱动逻辑集成电路
页数	文件大小	规格书
12页	395K
描述
PLL Based Clock Driver, 9658 Series, 10 True Output(s), 0 Inverted Output(s), CMOS, PQFP32, 7 X 7 MM, LEAD FREE, LQFP-32

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

MPC9658ACR2 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	7 X 7 MM, LEAD FREE, LQFP-32	针数：	32
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.25
Is Samacsys：	N	系列：	9658
输入调节：	DIFFERENTIAL	JESD-30 代码：	S-PQFP-G32
JESD-609代码：	e3	长度：	7 mm
逻辑集成电路类型：	PLL BASED CLOCK DRIVER	最大I（ol）：	0.024 A
湿度敏感等级：	3	功能数量：	1
反相输出次数：		端子数量：	32
实输出次数：	10	最高工作温度：	70 °C
最低工作温度：		输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	LQFP
封装等效代码：	QFP32,.35SQ,32	封装形状：	SQUARE
封装形式：	FLATPACK, LOW PROFILE	峰值回流温度（摄氏度）：	260
电源：	3.3 V	传播延迟（tpd）：	4 ns
认证状态：	Not Qualified	Same Edge Skew-Max（tskwd）：	0.12 ns
座面最大高度：	1.6 mm	子类别：	Clock Drivers
最大供电电压 (Vsup)：	3.465 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Matte Tin (Sn) - annealed	端子形式：	GULL WING
端子节距：	0.8 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	30	宽度：	7 mm
最小 fmax：	100 MHz	Base Number Matches：	1

MPC9658ACR2 数据手册

3.3V 1:10 LVCMOS PLL Clock Generator

MPC9658

NRND

DATASHEET

NRND – Not Recommend for New Designs

The MPC9658 is a 3.3 V compatible, 1:10 PLL based clock generator and

zero-delay buffer targeted for high performance low-skew clock distribution in

mid-range to high-performance telecom, networking and computing applications.

With output frequencies up to 250 MHz and output skews less than 120 ps the

device meets the needs of the most demanding clock applications. The

MPC9658 is specified for the temperature range of 0°C to +70°C.

MPC9658

Features

LOW VOLTAGE

•

1:10 PLL based low-voltage clock generator

Supports zero-delay operation

3.3 V LVCMOS 1:10

PLL CLOCK GENERATOR

3.3 V power supply

Generates clock signals up to 250 MHz

Maximum output skew of 120 ps

Differential LVPECL reference clock input

External PLL feedback

Drives up to 20 clock lines

FA SUFFIX

32-LEAD LQFP PACKAGE

CASE 873A-03

32-lead LQFP packaging

32-lead Pb-free Package Available

Pin and function compatible to the MPC958

NRND – Not Recommend for New Designs

AC SUFFIX

32-LEAD LQFP PACKAGE

Pb-FREE PACKAGE

CASE 873A-03

The MPC9658 utilizes PLL technology to frequency lock its outputs onto an

input reference clock. Normal operation of the MPC9658 requires the connection

of the QFB output to the feedback input to close the PLL feedback path (external

feedback). With the PLL locked, the output frequency is equal to the reference

frequency of the device and VCO_SEL selects the operating frequency range of

50 to 125 MHz or 100 to 250 MHz. The two available post-PLL dividers selected

by VCO_SEL (divide-by-2 or divide-by-4) and the reference clock frequency determine the VCO frequency. Both must be select-

ed to match the VCO frequency range. The internal VCO of the MPC9658 is running at either 2x or 4x of the reference clock

frequency.

The MPC9658 has a differential LVPECL reference input along with an external feedback input. The MPC9658 is ideal for use

as a zero delay, low skew fanout buffer. The device performance has been tuned and optimized for zero delay performance.

The PLL_EN and BYPASS controls select the PLL bypass configuration for test and diagnosis. In this configuration, the se-

lected input reference clock is bypassing the PLL and routed either to the output dividers or directly to the outputs. The PLL by-

pass configurations are fully static and the minimum clock frequency specification and all other PLL characteristics do not apply.

The outputs can be disabled (high-impedance) and the device reset by asserting the MR/OE pin. Asserting MR/OE also causes

the PLL to loose lock due to missing feedback signal presence at FB_IN. Deasserting MR/OE will enable the outputs and close

the phase locked loop, enabling the PLL to recover to normal operation.

The MPC9658 is fully 3.3 V compatible and requires no external loop filter components. The inputs (except PCLK) accept

LVCMOS except signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50  trans-

mission lines. For series terminated transmission lines, each of the MPC9658 outputs can drive one or two traces giving the de-

vices an effective fanout of 1:16. The device is packaged in a 7x7 mm²32-lead LQFP package.

MPC9658 REVISION 6 JANUARY 8, 2013

12 3 4 5 6 7...12

中文翻译

下载PDF

与MPC9658ACR2相关器件

型号	品牌	获取价格	描述	数据表
MPC9658FA	IDT	获取价格	PLL Based Clock Driver, 9658 Series, 10 True Output(s), 0 Inverted Output(s), CMOS, PQFP32
MPC9658FAR2	MOTOROLA	获取价格	PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7 MM, LQFP-32
MPC9658FAR2	NXP	获取价格	IC,1:10 OUTPUT,CMOS,QFP,32PIN,PLASTIC
MPC96877EP	IDT	获取价格	PLL Based Clock Driver, 96877 Series, 10 True Output(s), 0 Inverted Output(s), 6 X 6 MM, 0
MPC96877EP	NXP	获取价格	IC,1:10 OUTPUT, DIFFERENTIAL,LLCC,40PIN,PLASTIC
MPC96877EPR2	NXP	获取价格	96877 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC40, 6 X
MPC96877VK	MOTOROLA	获取价格	PLL Based Clock Driver, 10 True Output(s), 0 Inverted Output(s), PBGA52, 0.65 MM PITCH, LE
MPC96877VK	IDT	获取价格	PLL Based Clock Driver, 96877 Series, 10 True Output(s), 0 Inverted Output(s), PBGA52, 0.6
MPC96877VK	NXP	获取价格	96877 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52, 4.5
MPC96877VKR2	NXP	获取价格	96877 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52, 4.5

与MPC9658ACR2相关文章

国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

23
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

8
AMD宣布全球裁员约1000人，调整战略聚焦增长
2024-11-14

9
英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

32

产品中心

服务支持

精选活动

关于我们

帮助中心

MPC9658ACR2

MPC9658ACR2 技术参数

MPC9658ACR2 数据手册

与MPC9658ACR2相关器件

与MPC9658ACR2相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

MPC9658ACR2

MPC9658ACR2 技术参数

MPC9658ACR2 数据手册

与MPC9658ACR2相关器件

与MPC9658ACR2相关文章

您还可以找

您在本页遇到什么问题？