Datasheet > MPC973FA

MPC973FA

更新时间： 2024-11-12 19:46:39

品牌	Logo	应用领域
恩智浦 - NXP		驱动输出元件逻辑集成电路
页数	文件大小	规格书
16页	143K
描述
973 SERIES, PLL BASED CLOCK DRIVER, 13 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52, PLASTIC, LQFP-52

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MPC973FA 技术参数

是否Rohs认证：	不符合	生命周期：	Transferred
零件包装代码：	QFP	包装说明：	PLASTIC, LQFP-52
针数：	52	Reach Compliance Code：	not_compliant
HTS代码：	8542.39.00.01	风险等级：	5.24
系列：	973	输入调节：	DIFFERENTIAL MUX
JESD-30 代码：	S-PQFP-G52	JESD-609代码：	e0
长度：	10 mm	逻辑集成电路类型：	PLL BASED CLOCK DRIVER
湿度敏感等级：	2	功能数量：	1
反相输出次数：		端子数量：	52
实输出次数：	13	最高工作温度：	70 °C
最低工作温度：		输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	LQFP
封装形状：	SQUARE	封装形式：	FLATPACK, LOW PROFILE
认证状态：	Not Qualified	Same Edge Skew-Max（tskwd）：	0.55 ns
座面最大高度：	1.7 mm	最大供电电压 (Vsup)：	3.465 V
最小供电电压 (Vsup)：	3.135 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	QUAD
宽度：	10 mm	Base Number Matches：	1

MPC973FA 数据手册

ꢀ ꢁ ꢂ ꢁꢃ ꢁ ꢄꢅ

SEMICONDUCTOR TECHNICAL DATA

Order Number: MPC973/D

Rev. 1, 09/2001

ꢄ ꢆꢇ ꢈꢆꢉ ꢊꢋꢌ ꢍ ꢎ ꢄꢄ ꢏ ꢉꢆꢐ ꢑ ꢒꢓ ꢔꢕ ꢍ ꢓ

The MPC973 is a 3.3 V compatible, PLL based clock driver device

targeted for high performance CISC or RISC processor based systems.

With output frequencies of up to 125 MHz and skews of 550 ps the MPC973

is ideally suited for most synchronous systems. The device offer twelve low

skew outputs plus a feedback and sync output for added flexibility and ease

of system implementation.

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• Fully Integrated PLL

LOW VOLTAGE

PLL CLOCK DRIVER

• Output Frequency up to 125 MHz

• Compatible with PowerPC and Pentium Microprocessors

• LQFP Packaging

• 3.3 V V_CC

•

100ps Typical Cycle–to–Cycle Jitter

The MPC973 features an extensive level of frequency programmability

between the 12 outputs as well as the input vs output relationships. Using

the select lines output frequency ratios of 1:1, 2:1, 3:1, 3:2, 4:1, 4:3, 5:1, 5:2,

5:3, 6:1 and 6:5 between outputs can be realized by pulsing low one clock

edge prior to the coincident edges of the Qa and Qc outputs. The Sync

output will indicate when the coincident rising edges of the above

relationships will occur. The selectability of the feedback frequency is

independent of the output frequencies, this allows for very flexible

programming of the input reference vs output frequency relationship. The

output frequencies can be either odd or even multiples of the input

reference. In addition the output frequency can be less than the input

frequency for applications where a frequency needs to be reduced by a

non–binary factor. The Power–On Reset ensures proper programming if the

frequency select pins are set at power up. If the fselFB2 pin is held high, it

may be necessary to apply a reset after power–up to ensure

synchronization between the QFB output and the other outputs. The internal

power–on reset is designed to provide this function, but with power–up

conditions being dependent, it is difficult to guarantee. All other conditions of

the fsel pins will automatically synchronize during PLL lock acquisition.

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FA SUFFIX

52–LEAD LQFP PACKAGE

CASE 848D-03

The MPC973 offers a very flexible output enable/disable scheme. This enable/disable scheme helps facilitate system debug as

well as provide unique opportunities for system power down schemes to meet the requirements of “green” class machines. The

MPC973 allows for the enabling of each output independently via a serial input port. When disabled or “frozen” the outputs will be

locked in the “LOW” state, however the internal state machines will continue to run. Therefore when “unfrozen” the outputs will

activate synchronous and in phase with those outputs which were not frozen. The freezing and unfreezing of outputs occurs only

when they are already in the “LOW” state, thus the possibility of runt pulse generation is eliminated. A power-on reset will ensure

that upon power up all of the outputs will be active. Note that all of the control inputs on the MPC973 have internal pull–up resistors.

The MPC973 is fully 3.3 V compatible and requires no external loop filter components. All inputs accept LVCMOS/LVTTL

compatible levels while the outputs provide LVCMOS levels with the capability to drive 50 Ω transmission lines. For series

terminated lines each MPC973 output can drive two 50 Ω lines in parallel thus effectively doubling the fanout of the device.

The MPC973 can consume significant power in some configurations. Users are encouraged to review Application Note

AN1545/D in the Advanced Clock Drivers Device Data book (DL207/D) for a discussion on the thermal issues with the MPC family

of clock drivers.

PowerPC is a trademark of International Business Machines Corporation. Pentium is a trademark of Intel Corporation.

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 Motorola, Inc. 2001

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与MPC973FA相关器件

型号	品牌	获取价格	描述	数据表
MPC973FAR2	IDT	获取价格	PLL Based Clock Driver, 973 Series, 13 True Output(s), 0 Inverted Output(s), PQFP52, PLAST
MPC974	MOTOROLA	获取价格	LOW VOLTAGE PLL CLOCK DRIVER
MPC974FA	NXP	获取价格	974 SERIES, PLL BASED CLOCK DRIVER, 14 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52, PLAST
MPC974FA	IDT	获取价格	PLL Based Clock Driver, 974 Series, 14 True Output(s), 0 Inverted Output(s), CMOS, PQFP52,
MPC974FA	MOTOROLA	获取价格	PLL Based Clock Driver, 974 Series, 14 True Output(s), 0 Inverted Output(s), CMOS, PQFP52,
MPC974FAR2	NXP	获取价格	974 SERIES, PLL BASED CLOCK DRIVER, 14 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52, PLAST
MPC974FAR2	MOTOROLA	获取价格	974 SERIES, PLL BASED CLOCK DRIVER, 14 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52, LQFP-
MPC9772	IDT	获取价格	3.3V 1:12 LVCMOS PLL Clock Generator Internal Power-On Reset
MPC9772	MOTOROLA	获取价格	3.3V 1:12 LVCMOS PLL Clock Generator
MPC9772AE	IDT	获取价格	TQFP-52, Tray

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