Datasheet > MPC974FAR2

MPC974FAR2

更新时间： 2024-09-23 19:57:15

品牌	Logo	应用领域
恩智浦 - NXP		驱动输出元件逻辑集成电路
页数	文件大小	规格书
6页	294K
描述
974 SERIES, PLL BASED CLOCK DRIVER, 14 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52, PLASTIC, LQFP-52

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MPC974FAR2 技术参数

是否Rohs认证：	不符合	生命周期：	Transferred
零件包装代码：	QFP	包装说明：	PLASTIC, LQFP-52
针数：	52	Reach Compliance Code：	not_compliant
HTS代码：	8542.39.00.01	风险等级：	5.22
系列：	974	输入调节：	MUX
JESD-30 代码：	S-PQFP-G52	JESD-609代码：	e0
长度：	10 mm	逻辑集成电路类型：	PLL BASED CLOCK DRIVER
湿度敏感等级：	2	功能数量：	1
反相输出次数：		端子数量：	52
实输出次数：	14	最高工作温度：	70 °C
最低工作温度：		输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	LQFP
封装形状：	SQUARE	封装形式：	FLATPACK, LOW PROFILE
认证状态：	Not Qualified	Same Edge Skew-Max（tskwd）：	0.35 ns
座面最大高度：	1.7 mm	最大供电电压 (Vsup)：	3.465 V
最小供电电压 (Vsup)：	3.135 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	QUAD	宽度：	10 mm
Base Number Matches：	1

MPC974FAR2 数据手册

Freescale Semiconductor, Inc.

SEMICONDUCTOR TECHNICAL DATA

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The MPC974 is a fully integrated PLL based clock generator and clock

distribution chip which operates from a 3.3V supply. The MPC974 is ideal-

ly suited for high speed, timing critical designs which need a high level of

clock fanout. The device features 15 high drive LVCMOS outputs, each

output has the capability of driving a 50Ω parallel terminated transmission

line or two 50Ω series terminated transmission lines on the incident edge.

See Upgrade Product – MPC9774

LOW VOLTAGE

PLL CLOCK DRIVER

• Fully Integrated PLL

• Two Reference Clock Inputs for Redundant Clock Applications

• High Impedance Output Control

• Logic Enable on the Outputs

• 3.3V V_CCSupply

• Output Frequency Configurable

• LQFP Packaging

•

100ps Typical Cycle–to–Cycle Jitter

The MPC974 features 3 independent frequency programmable banks

of outputs. The frequency programmability offers the capability of estab-

lishing output frequency relationships of 1:1, 2:1, 3:1, 3:2 and 3:2:1. In

addition, the device features a separate feedback output which allows for

a wide variety of input/output frequency multiplication alternatives. The

VCO_Sel pin provides an extended VCO lock range for added flexibility

and general purpose usage.

FA SUFFIX

52–LEAD LQFP PACKAGE

CASE 848D-03

The TCLK0 and TCLK1 inputs provide a method for dynamically

switching the PLL between two different clock sources. The PLL has been

optimized to provide small deviations in output pulse width and well con-

trolled, slow transition back to lock when the inputs are switched between

two references that are equal in frequency but out of phase with each

other. This feature makes the MPC974 a solution for fault tolerant applica-

tions which require redundant clock sources.

For designs in which fault tolerance is critical, other products may provide more control over the clock switch functions. For

these features please refer to the MPC993 datasheet.

All of the control pins are LVTTL/LVCMOS level inputs. The Fsel pins control the VCO divide ratios that are applied to the

various output banks and the feedback output. The MR input will reset the internal flip flops and place the outputs in high

impedance when driven LOW. The OE pin will force all of the outputs except the feedback output LOW to allow for acquiring

phase lock prior to providing clocks to the rest of the system. Note that the OE pin is not synchronized to the internal clock. As a

result, the initial pulse after de–assertion of the OE pin may be distorted. The PLL_En pin allows the PLL to be bypassed for

board level functional test. When bypassed the signal on the selected TCLK will be routed around the PLL and will drive the

internal dividers directly.

The MPC974 is packaged in the 52–lead LQFP package to provide optimum electrical performance as well as minimize board

space requirements. The device is specified for 3.3V V_CC

Rev 3

210

MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA

For More Information On This Product,

Go to: www.freescale.com

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与MPC974FAR2相关器件

型号	品牌	获取价格	描述	数据表
MPC9772	IDT	获取价格	3.3V 1:12 LVCMOS PLL Clock Generator Internal Power-On Reset
MPC9772	MOTOROLA	获取价格	3.3V 1:12 LVCMOS PLL Clock Generator
MPC9772AE	IDT	获取价格	TQFP-52, Tray
MPC9772AER2	MOTOROLA	获取价格	240MHz, OTHER CLOCK GENERATOR, PQFP52, LQFP-52
MPC9772FA	IDT	获取价格	Clock Generator, 230MHz, CMOS, PQFP52, LQFP-52
MPC9772FA	MOTOROLA	获取价格	240MHz, OTHER CLOCK GENERATOR, PQFP52, LQFP-52
MPC9772FAR2	MOTOROLA	获取价格	240MHz, OTHER CLOCK GENERATOR, PQFP52, LQFP-52
MPC9772FAR2	IDT	获取价格	Clock Generator, 240MHz, CMOS, PQFP52, LQFP-52
MPC9773	FREESCALE	获取价格	3.3 V 1:12 LVCMOS PLL Clock Generator
MPC9773AE	FREESCALE	获取价格	3.3 V 1:12 LVCMOS PLL Clock Generator

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