Datasheet > MPC9772FA

MPC9772FA

更新时间： 2024-11-11 21:00:07

品牌	Logo	应用领域
艾迪悌 - IDT		时钟外围集成电路晶体
页数	文件大小	规格书
17页	242K
描述
Clock Generator, 230MHz, CMOS, PQFP52, LQFP-52

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MPC9772FA 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	LQFP-52	针数：	52
Reach Compliance Code：	not_compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.21
JESD-30 代码：	S-PQFP-G52	JESD-609代码：	e0
长度：	10 mm	湿度敏感等级：	3
端子数量：	52	最高工作温度：	85 °C
最低工作温度：	-40 °C	最大输出时钟频率：	230 MHz
封装主体材料：	PLASTIC/EPOXY	封装代码：	LQFP
封装等效代码：	QFP52,.47SQ	封装形状：	SQUARE
封装形式：	FLATPACK, LOW PROFILE	峰值回流温度（摄氏度）：	240
电源：	3.3 V	主时钟/晶体标称频率：	250 MHz
认证状态：	Not Qualified	座面最大高度：	1.7 mm
子类别：	Clock Generators	最大压摆率：	15 mA
最大供电电压：	3.465 V	最小供电电压：	3.135 V
标称供电电压：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn85Pb15)	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	20	宽度：	10 mm
uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, OTHER	Base Number Matches：	1

MPC9772FA 数据手册

3.3V 1:12 LVCMOS PLL Clock Generator

MPC9772

DATA SHEET

PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES SEPTEMBER 7, 2016

The MPC9772 is a 3.3 V compatible, 1:12 PLL based clock generator targeted

for high performance low-skew clock distribution in mid-range to

high-performance networking, computing and telecom applications. With output

frequencies up to 240 MHz and output skews less than 250 ps the device meets

the needs of the most demanding clock applications.

MPC9772

Features

•

1:12 PLL Based Low-Voltage Clock Generator

3.3 V Power Supply

3.3 V 1:12 LVCMOS

PLL CLOCK GENERATOR

Internal Power-On Reset

Generates Cock Signals Up to 240 MHz

Maximum Output Skew of 250 ps

On-Chip Crystal Oscillator Clock Reference

Two LVCMOS PLL Reference Clock Inputs

External PLL Feedback Supports Zero-Delay Capability

Various Feedback and Output Dividers (See Applications Information

Section)

AE SUFFIX

52-LEAD LQFP PACKAGE

Pb-FREE PACKAGE

CASE 848D-03

•

Supports Up to Three Individual Generated Output Clock Frequencies

Synchronous Output Clock Stop Circuitry for Each Individual Output for

Power Down Support

•

Drives Up to 24 Clock Lines

Ambient Temperature Range 0C to +70C

Pin and Function Compatible To the MPC972

52-Lead Pb-Free Package

For drop in replacement use 87972DYI-147

Functional Description

The MPC9772 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the

MPC9772 requires the connection of the PLL feedback output QFB to feedback input FB_IN to close the PLL feedback path. The

reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to match

the VCO frequency range. The MPC9772 features an extensive level of frequency programmability between the 12 outputs as

well as the output to input relationships, for instance 1:1, 2:1, 3:1, 3:2, 4:1, 4:3, 5:1, 5:2, 5:3, 5:4, 5:6, 6:1, 8:1, and 8:3.

The QSYNC output will indicate when the coincident rising edges of the above relationships will occur. The selectability of the

feedback frequency is independent of the output frequencies. This allows for very flexible programming of the input reference

versus output frequency relationship. The output frequencies can be either odd or even multiples of the input reference. In addi-

tion the output frequency can be less than the input frequency for applications where a frequency needs to be reduced by a non-

binary factor. The MPC9772 also supports the 180 phase shift of one of its output banks with respect to the other output banks.

The QSYNC outputs reflects the phase relationship between the QA and QC outputs and can be used for the generation of sys-

tem baseline timing signals.

The REF_SEL pin selects the internal crystal oscillator or the LVCMOS compatible inputs as the reference clock signal. Two

alternative LVCMOS compatible clock inputs are provided for clock redundancy support. The PLL_EN control selects the PLL

bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is routed directly to the output

dividers bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL char-

acteristics do not apply.

The outputs can be individually disabled (stopped in logic low state) by programming the serial CLOCK_STOP interface of the

MPC9772. The MPC9772 has an internal power-on reset.

The MPC9772 is fully 3.3 V compatible and requires no external loop filter components. All inputs (except XTAL) accept

LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50  transmission

lines. For series terminated transmission lines, each of the MPC9772 outputs can drive one or two traces giving the devices an

effective fanout of 1:24. The device is pin and function compatible to the MPC972 and is packaged in a 52-lead LQFP package.

MPC9772 REVISION 8 3/16/16

12 3 4 5 6 7...17

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MPC9772FA 替代型号

型号	品牌	替代类型	描述	数据表
87972DYILF	IDT	类似代替	LOW SKEW, 1-TO-12 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER

与MPC9772FA相关器件

型号	品牌	获取价格	描述	数据表
MPC9772FAR2	MOTOROLA	获取价格	240MHz, OTHER CLOCK GENERATOR, PQFP52, LQFP-52
MPC9772FAR2	IDT	获取价格	Clock Generator, 240MHz, CMOS, PQFP52, LQFP-52
MPC9773	FREESCALE	获取价格	3.3 V 1:12 LVCMOS PLL Clock Generator
MPC9773AE	FREESCALE	获取价格	3.3 V 1:12 LVCMOS PLL Clock Generator
MPC9773FA	FREESCALE	获取价格	3.3 V 1:12 LVCMOS PLL Clock Generator
MPC9773FA	MOTOROLA	获取价格	PLL BASED CLOCK DRIVER, 13 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52, PLASTIC, LQFP-52
MPC9773FAR2	IDT	获取价格	PLL Based Clock Driver, 9773 Series, 13 True Output(s), 0 Inverted Output(s), CMOS, PQFP52
MPC9773FAR2	MOTOROLA	获取价格	PLL BASED CLOCK DRIVER, 13 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52, PLASTIC, LQFP-52
MPC9774	MOTOROLA	获取价格	3.3V / 2,5V 1:14 LVCMOS PLL CLOCK GENERATOR
MPC9774AE	NXP	获取价格	9774 SERIES, PLL BASED CLOCK DRIVER, 14 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52, PLAS

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