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MPC980FA PDF预览

MPC980FA

更新时间: 2024-09-24 19:11:35
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
7页 474K
描述
Processor Specific Clock Generator, 66MHz, PQFP52, PLASTIC, LQFP-52

MPC980FA 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:QFP
包装说明:LQFP,针数:52
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.28
JESD-30 代码:S-PQFP-G52JESD-609代码:e0
长度:10 mm端子数量:52
最高工作温度:70 °C最低工作温度:
最大输出时钟频率:66 MHz封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE峰值回流温度(摄氏度):240
主时钟/晶体标称频率:14.31818 MHz认证状态:Not Qualified
座面最大高度:1.7 mm最大供电电压:3.465 V
最小供电电压:3.135 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:0.65 mm
端子位置:QUAD处于峰值回流温度下的最长时间:20
宽度:10 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches:1

MPC980FA 数据手册

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DATA SHEET  
MPC980  
Dual 3.3 V PLL Clock Generator  
The MPC980 is a 3.3V dual PLL clock generator targeted for high end  
Pentium and PowerPC 603/604 personal computers. The MPC980  
synthesizes processor as well as PCI clocks from a 14.31818MHz  
external crystal. In addition the device provides two buffered outputs of  
the 14.31818MHz crystal as well as a 40MHz SCSI clock, a 24MHz floppy  
clock and a 12MHz keyboard clock. One of the buffered 14.31818MHz  
outputs can be configured to provide a 16MHz output rather than the  
second copy of the 14.31818MHz output.  
DUAL 3.3V PLL  
CLOCK GENERATOR  
Provides Processor and System Clocks for Pentium Designs  
Provides Processor and System Clocks for PowerPC 603/604  
Designs  
Two Fully Integrated Phase–Locked Loops  
Cycle–to–Cycle Jitter of ±150ps  
Operates from 3.3V Supply  
52–Lead LQFP Packaging  
The processor clock outputs of the MPC980 can be programmed to  
provide 50, 60 or 66MHz. Under all processor output frequencies the PCI  
clock outputs will be equal to one half the processor clock outputs. The  
PCI outputs will run synchronously to the processor clock outputs. There  
are a total of ten output clocks which can be split into a group of four and a  
group of six. Either group can be configured as processor or PCI clocks.  
Each of the outputs can drive two series terminated transmission lines  
allowing for the driving of up to twelve independent processor loads and  
eight PCI clock loads. A pin selectable option is available to delay the PCI  
clock outputs relative to the processor clocks. The amount of delay is a  
function of the processor clock frequency and varies from 2ns to 6ns.  
FA SUFFIX  
52–LEAD LQFP PACKAGE  
CASE 848D–03  
The output jitter of the the PLL at 66MHz output is ±150ps peak–to–peak, cycle–to–cycle (the worst case deviation of the clock  
period is guaranteed to be less than ±150ps). The skews between one processor clock and any other processor clock (or one  
PCI clock to any other PCI clock) is 350ps. The worst case skew between the processor clocks and the PCI clocks is 500ps.  
An output enable pin is provided to tristate all of the outputs for board level test. In addition a testing mode is provided to allow  
for the bypass of the PLL’s for board level functional debug.  
Pentium is a trademark of Intel Corporation. PowerPC is a trademark of International Business  
IDT™ Dual 3.3 V PLL Clock Generator  
MPC980  
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc  
1

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