Datasheet > MPC97R72FA

MPC97R72FA

更新时间： 2024-09-24 20:56:31

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		时钟外围集成电路晶体
页数	文件大小	规格书
16页	242K
描述
240MHz, OTHER CLOCK GENERATOR, PQFP52, LQFP-52

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MPC97R72FA 技术参数

生命周期：	Obsolete	包装说明：	LQFP-52
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.84
其他特性：	ALSO OPERATES WITH 2.5V SUPPLY	JESD-30 代码：	S-PQFP-G52
长度：	10 mm	端子数量：	52
最高工作温度：	85 °C	最低工作温度：
最大输出时钟频率：	240 MHz	封装主体材料：	PLASTIC/EPOXY
封装代码：	LQFP	封装等效代码：	QFP52,.47SQ
封装形状：	SQUARE	封装形式：	FLATPACK, LOW PROFILE
电源：	2.5/3.3 V	主时钟/晶体标称频率：	25 MHz
认证状态：	Not Qualified	座面最大高度：	1.7 mm
子类别：	Clock Generators	最大供电电压：	3.465 V
最小供电电压：	3.135 V	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	OTHER	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	QUAD
宽度：	10 mm	uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, OTHER
Base Number Matches：	1

MPC97R72FA 数据手册

Order Number: MPC97R72/D

Rev 0, 04/2002

SEMICONDUCTOR TECHNICAL DATA

The MPC97R72 is a 3.3V or 2.5V compatible, 1:12 PLL based clock

generator targeted for high performance low-skew clock distribution in

mid-range to high-performance networking, computing and telecom

applications. With output frequencies up to 240 MHz and output skews

less than 300 ps the device meets the needs of the most demanding

clock applications.

3.3V/2.5V 1:12 LVCMOS

PLL CLOCK GENERATOR

Features

• 1:12 PLL based low-voltage clock generator

• 2.5V or 3.3V power supply

• Internal power–on reset

• Generates clock signals up to 240 MHz

• Maximum output skew of 300 ps

• On-chip crystal oscillator clock reference

• Two LVCMOS PLL reference clock inputs

• External PLL feedback supports zero-delay capability

• Various feedback and output dividers (see application section)

• Supports up to three individual generated output clock frequencies

FA SUFFIX

52 LEAD LQFP PACKAGE

CASE 848D

• Synchronous output clock stop circuitry for each individual output for

power down support

• Drives up to 24 clock lines

• Ambient temperature range 0°C to +85°C

• Pin and function compatible to the MPC972

Functional Description

The MPC97R72 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the

MPC97R72 requires the connection of the PLL feedback output QFB to feedback input FB_IN to close the PLL feedback path.

The reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to

match the VCO frequency range. The MPC97R72 features an extensive level of frequency programmability between the 12

outputs as well as the output to input relationships, for instance 1:1, 2:1, 3:1, 3:2, 4:1, 4:3, 5:1, 5:2, 5:3, 5:4, 5:6, 6:1, 8:1 and 8:3.

The QSYNC output will indicate when the coincident rising edges of the above relationships will occur. The selectability of the

feedback frequency is independent of the output frequencies. This allows for very flexible programming of the input reference

versus output frequency relationship. The output frequencies can be either odd or even multiples of the input reference. In

addition the output frequency can be less than the input frequency for applications where a frequency needs to be reduced by a

non–binary factor. The MPC97R72 also supports the 180º phase shift of one of its output banks with respect to the other output

banks. The QSYNC outputs reflects the phase relationship between the QA and QC outputs and can be used for the generation

of system baseline timing signals.

The REF_SEL pin selects the internal crystal oscillator or the LVCMOS compatible inputs as the reference clock signal. Two

alternative LVCMOS compatible clock inputs are provided for clock redundancy support. The PLL_EN control selects the PLL

bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is routed directly to the output

dividers bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL

characteristics do not apply.

The outputs can be individually disabled (stopped in logic low state) by programming the serial CLOCK_STOP interface of the

MPC97R72. The MPC97R72 has an internal power–on reset.

The MPC97R72 is fully 2.5V and 3.3V compatible and requires no external loop filter components. All inputs (except XTAL)

accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50

transmission lines. For series terminated transmission lines, each of the MPC97R72 outputs can drive one or two traces giving

the devices an effective fanout of 1:24. The device is pin and function compatible to the MPC972 and is packaged in a 52-lead

LQFP package.

1. Final specification of this parameter is pending characterization.

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

Motorola, Inc. 2002

12 3 4 5 6 7...16

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与MPC97R72FA相关器件

型号	品牌	获取价格	描述	数据表
MPC97R73FA	MOTOROLA	获取价格	PLL Based Clock Driver, 12 True Output(s), 0 Inverted Output(s), CMOS, PQFP52, LQFP-52
MPC97R74FA	MOTOROLA	获取价格	PLL BASED CLOCK DRIVER, 14 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52, LQFP-52
MPC980	MOTOROLA	获取价格	DUAL 3.3V PLL CLOCK GENERATOR
MPC980FA	IDT	获取价格	Processor Specific Clock Generator, 66MHz, PQFP52, PLASTIC, LQFP-52
MPC980FA	MOTOROLA	获取价格	66MHz, PROC SPECIFIC CLOCK GENERATOR, PQFP52, PLASTIC, LQFP-52
MPC980FAR2	MOTOROLA	获取价格	66MHz, PROC SPECIFIC CLOCK GENERATOR, PQFP52, PLASTIC, LQFP-52
MPC9817	FREESCALE	获取价格	Clock Generator for PowerQUICC and PowerPC Microprocessors and Microcontrollers
MPC9817ENR2	IDT	获取价格	Processor Specific Clock Generator, 66MHz, CMOS, PDSO20, LEAD FREE, SSOP-20
MPC9817ENR2	NXP	获取价格	66MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO20, LEAD FREE, SSOP-20
MPC9817SD	NXP	获取价格	66MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO20, SSOP-20

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