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MPC97H73FA PDF预览

MPC97H73FA

更新时间: 2024-11-21 20:10:55
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
17页 584K
描述
PLL Based Clock Driver, 97H Series, 12 True Output(s), 0 Inverted Output(s), CMOS, PQFP52, LQFP-52

MPC97H73FA 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFP
包装说明:LQFP-52针数:52
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.27
系列:97H输入调节:DIFFERENTIAL MUX
JESD-30 代码:S-PQFP-G52JESD-609代码:e0
长度:10 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
最大I(ol):0.024 A湿度敏感等级:3
功能数量:1反相输出次数:
端子数量:52实输出次数:12
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装等效代码:QFP52,.47SQ
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE
峰值回流温度(摄氏度):240电源:3.3 V
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.25 ns
座面最大高度:1.7 mm子类别:Clock Drivers
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:0.65 mm端子位置:QUAD
处于峰值回流温度下的最长时间:20宽度:10 mm
最小 fmax:100 MHzBase Number Matches:1

MPC97H73FA 数据手册

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DATA SHEET  
3.3V 1:12 LVCMOS PLL Clock  
MPC97H73  
Generator  
The MPC97H73 is a 3.3V compatible, 1:12 PLL based clock generator  
targeted for high performance low-skew clock distribution in mid-range to  
high-performance networking, computing and telecom applications. With  
output frequencies up to 240 MHz and output skews less than 250 ps the  
device meets the needs of the most demanding clock applications.  
3.3V 1:12 LVCMOS  
PLL CLOCK GENERATOR  
Features  
1:12 PLL based low-voltage clock generator  
3.3V power supply  
Internal power–on reset  
Generates clock signals up to 240 MHz  
Maximum output skew of 250 ps  
Differential PECL reference clock input  
Two LVCMOS PLL reference clock inputs  
External PLL feedback supports zero-delay capability  
Various feedback and output dividers (see application section)  
Supports up to three individual generated output clock frequencies  
FA SUFFIX  
52 LEAD LQFP PACKAGE  
CASE 848D  
Synchronous output clock stop circuitry for each individual output for  
power down support  
Drives up to 24 clock lines  
Ambient temperature range 0°C to +70°C  
Pin and function compatible to the MPC973  
Functional Description  
The MPC97H73 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the  
MPC97H73 requires the connection of the PLL feedback output QFB to feedback input FB_IN to close the PLL feedback path.  
The reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to  
match the VCO frequency range. The MPC97H73 features an extensive level of frequency programmability between the 12  
outputs as well as the output to input relationships, for instance 1:1, 2:1, 3:1, 3:2, 4:1, 4:3, 5:1, 5:2, 5:3, 5:4, 5:6, 6:1, 8:1 and 8:3.  
The QSYNC output will indicate when the coincident rising edges of the above relationships will occur. The selectability of the  
feedback frequency is independent of the output frequencies. This allows for very flexible programming of the input reference  
versus output frequency relationship. The output frequencies can be either odd or even multiples of the input reference. In  
addition the output frequency can be less than the input frequency for applications where a frequency needs to be reduced by a  
non–binary factor. The MPC97H73 also supports the 180° phase shift of one of its output banks with respect to the other output  
banks. The QSYNC outputs reflects the phase relationship between the QA and QC outputs and can be used for the generation  
of system baseline timing signals.  
The REF_SEL pin selects the LVPECL or the LVCMOS compatible inputs as the reference clock signal. Two alternative  
LVCMOS compatible clock inputs are provided for clock redundancy support. The PLL_EN control selects the PLL bypass  
configuration for test and diagnosis. In this configuration, the selected input reference clock is routed directly to the output dividers  
bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL characteristics  
do not apply.  
The outputs can be individually disabled (stopped in logic low state) by programming the serial CLOCK_STOP interface of the  
MPC97H73. The MPC97H73 has an internal power–on reset.  
The MPC97H73 is fully 3.3V compatible and requires no external loop filter components. All inputs (except PCLK) accept  
LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 W transmission  
lines. For series terminated transmission lines, each of the MPC97H73 outputs can drive one or two traces giving the devices an  
effective fanout of 1:24. The device is pin and function compatible to the MPC973 and is packaged in a 52-lead LQFP package.  
IDT™ 3.3V 1:12 LVCMOS PLL Clock Generator  
MPC97H73  
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc  
1

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