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MPC980 PDF预览

MPC980

更新时间: 2024-09-23 22:51:11
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 时钟发生器
页数 文件大小 规格书
7页 142K
描述
DUAL 3.3V PLL CLOCK GENERATOR

MPC980 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
The MPC980 is a 3.3V dual PLL clock generator targeted for high end  
Pentium and PowerPC 603/604 personal computers. The MPC980  
synthesizes processor as well as PCI clocks from a 14.31818MHz  
external crystal. In addition the device provides two buffered outputs of  
the 14.31818MHz crystal as well as a 40MHz SCSI clock, a 24MHz floppy  
clock and a 12MHz keyboard clock. One of the buffered 14.31818MHz  
outputs can be configured to provide a 16MHz output rather than the  
second copy of the 14.31818MHz output.  
DUAL 3.3V PLL  
CLOCK GENERATOR  
Provides Processor and System Clocks for Pentium Designs  
Provides Processor and System Clocks for PowerPC 603/604  
Designs  
Two Fully Integrated Phase–Locked Loops  
Cycle–to–Cycle Jitter of ±150ps  
Operates from 3.3V Supply  
52–Lead LQFP Packaging  
The processor clock outputs of the MPC980 can be programmed to  
provide 50, 60 or 66MHz. Under all processor output frequencies the PCI  
clock outputs will be equal to one half the processor clock outputs. The  
PCI outputs will run synchronously to the processor clock outputs. There  
are a total of ten output clocks which can be split into a group of four and a  
group of six. Either group can be configured as processor or PCI clocks.  
Each of the outputs can drive two series terminated transmission lines  
allowing for the driving of up to twelve independent processor loads and  
eight PCI clock loads. A pin selectable option is available to delay the PCI  
clock outputs relative to the processor clocks. The amount of delay is a  
function of the processor clock frequency and varies from 2ns to 6ns.  
FA SUFFIX  
52–LEAD LQFP PACKAGE  
CASE 848D–03  
The output jitter of the the PLL at 66MHz output is ±150ps peak–to–peak, cycle–to–cycle (the worst case deviation of the clock  
period is guaranteed to be less than ±150ps). The skews between one processor clock and any other processor clock (or one  
PCI clock to any other PCI clock) is 350ps. The worst case skew between the processor clocks and the PCI clocks is 500ps.  
An output enable pin is provided to tristate all of the outputs for board level test. In addition a testing mode is provided to allow  
for the bypass of the PLL’s for board level functional debug.  
Pentium is a trademark of Intel Corporation. PowerPC is a trademark of International Business  
Machines Corporation.  
1/98  
REV 2  
Motorola, Inc. 1998  

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