Datasheet > MPC9774FAR2

MPC9774FAR2

更新时间： 2024-11-12 19:49:43

品牌	Logo	应用领域
艾迪悌 - IDT		驱动逻辑集成电路
页数	文件大小	规格书
14页	192K
描述
PLL Based Clock Driver, 9774 Series, 14 True Output(s), 0 Inverted Output(s), CMOS, PQFP52, PLASTIC, LQFP-52

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MPC9774FAR2 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	PLASTIC, LQFP-52	针数：	52
Reach Compliance Code：	not_compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.24
其他特性：	CAN ALSO OPERATE AT 3.3V SUPPLY	系列：	9774
输入调节：	MUX	JESD-30 代码：	S-PQFP-G52
JESD-609代码：	e0	长度：	10 mm
逻辑集成电路类型：	PLL BASED CLOCK DRIVER	最大I（ol）：	0.024 A
湿度敏感等级：	3	功能数量：	1
反相输出次数：		端子数量：	52
实输出次数：	14	最高工作温度：	70 °C
最低工作温度：		输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	LQFP
封装等效代码：	QFP52,.47SQ	封装形状：	SQUARE
封装形式：	FLATPACK, LOW PROFILE	峰值回流温度（摄氏度）：	240
电源：	3.3 V	Prop。Delay @ Nom-Sup：	0.1 ns
认证状态：	Not Qualified	Same Edge Skew-Max（tskwd）：	0.175 ns
座面最大高度：	1.7 mm	子类别：	Clock Drivers
最大供电电压 (Vsup)：	3.465 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn85Pb15)	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	20	宽度：	10 mm
最小 fmax：	50 MHz	Base Number Matches：	1

MPC9774FAR2 数据手册

3.3 V 1:14 LVCMOS PLL Clock Generator

MPC9774

PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES SEPTEMBER 7, 2016

DATASHEET

3.3 V 1:14 LVCMOS PLL Clock

Generator

MPC9774

The MPC9774 is a 3.3 V compatible, 1:14 PLL based clock generator targeted

for high performance low-skew clock distribution in mid-range to high-

performance networking, computing and telecom applications. With output

frequencies up to 125 MHz and output skews less than 175 ps the device meets

the needs of the most demanding clock applications.

3.3 V 1:14 LVCMOS

PLL CLOCK GENERATOR

Features

•

1:14 PLL Based Low-Voltage Clock Generator

3.3 V Power Supply

Internal Power-On Reset

Generates Clock Signals Up to 125 MHz

Maximum Output Skew of 175 ps

Two LVCMOS PLL Reference Clock Inputs

External PLL Feedback Supports Zero-Delay Capability

Various Feedback and Output Dividers (See Applications Information)

Supports Up to Three Individual Generated Output Clock Frequencies

Drives Up to 28 Clock Lines

AE SUFFIX

52-LEAD LQFP PACKAGE

Pb-FREE PACKAGE

CASE 848D-03

Ambient Temperature Range 0°C to +70°C

Pin and Function Compatible to the MPC974

52-Lead LQFP Package, Pb-free

For drop in replacement use 87974

The MPC9774 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the

MPC9774 requires the connection of the PLL feedback output QFB to feedback input FB_IN to close the PLL feedback path. The

reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to match

the VCO frequency range.

The MPC9774 features frequency programmability between the three output banks outputs as well as the output to input re-

lationships. Output frequency ratios of 1:1, 2:1, 3:1, 3:2 and 3:2:1 can be realized. Additionally, the device supports a separate

configurable feedback output which allows for a wide variety of input/output frequency multiplication alternatives. The VCO_SEL

pin provides an extended PLL input reference frequency range.

The REF_SEL pin selects the internal crystal oscillator or the LVCMOS compatible inputs as the reference clock signal. Two

alternative LVCMOS compatible clock inputs are provided for clock redundancy support. The PLL_EN control selects the PLL

bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is routed directly to the output

dividers bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL char-

acteristics do not apply.

The MPC9774 has an internal power-on reset.

The MPC9774 is fully 3.3 V compatible and requires no external loop filter components. All inputs (except XTAL) accept

LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50  transmission

lines. For series terminated transmission lines, each of the MPC9774 outputs can drive one or two traces giving the devices an

effective fanout of 1:12. The device is pin and function compatible to the MPC974 and is packaged in a 52-lead LQFP package.

MPC9774 REVISION 5 3/16/16

12 3 4 5 6 7...14

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与MPC9774FAR2相关器件

型号	品牌	获取价格	描述	数据表
MPC97H73AE	IDT	获取价格	PLL Based Clock Driver, 97H Series, 13 True Output(s), 0 Inverted Output(s), PQFP52, PLAST
MPC97H73AE	NXP	获取价格	97H SERIES, PLL BASED CLOCK DRIVER, 13 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52, PLAST
MPC97H73AER2	NXP	获取价格	PLL Based Clock Driver, 13 True Output(s), 0 Inverted Output(s), PQFP52, LQFP-52
MPC97H73FA	NXP	获取价格	PLL BASED CLOCK DRIVER, 13 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52, LQFP-52
MPC97H73FA	IDT	获取价格	PLL Based Clock Driver, 97H Series, 12 True Output(s), 0 Inverted Output(s), CMOS, PQFP52,
MPC97H73FAR2	MOTOROLA	获取价格	PLL Based Clock Driver, 13 True Output(s), 0 Inverted Output(s), CMOS, PQFP52, LQFP-52
MPC97H73FAR2	NXP	获取价格	IC,1:12 OUTPUT,CMOS,QFP,52PIN,PLASTIC
MPC97H74AER2	IDT	获取价格	PLL Based Clock Driver, 97H Series, 14 True Output(s), 0 Inverted Output(s), CMOS, PQFP52,
MPC97R72FA	MOTOROLA	获取价格	240MHz, OTHER CLOCK GENERATOR, PQFP52, LQFP-52
MPC97R73FA	MOTOROLA	获取价格	PLL Based Clock Driver, 12 True Output(s), 0 Inverted Output(s), CMOS, PQFP52, LQFP-52

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